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VFX MEMORY MANAGER

                                    ;***************************************************************************
                                    ;
                                    ; File Name		:'memory.asm"
                                    ; Title			:Memory Manager for VFX's DataLog
                                    ; Date			:2003.08.03.
                                    ; Version		:1.0.0
                                    ; Support telephone	:+36-70-333-4034,  old: +36-30-9541-658 VFX
                                    ; Support fax		:
                                    ; Support Email		:info@vfx.hu
                                    ; Target MCU		:ATmega128
                                    ;
                                    ;***************************************************************************
                                    ;	D E S C R I P T I O N
                                    ;
                                    ;
                                    ; MCB
                                    ; 0. byte - Type/Flag
                                    ;		7. =1 last block
                                    ;		6. =1 first block
                                    ;		5. =1 used block
                                    ;		4. = nc
                                    ;		3:0 = process number Hi part
                                    ; 1. byte - process number low part
                                    ; 2. word - low part of length
                                    ; 4. byte - hi part of length
                                    ; 5. word - low part offset of prev. MCB  
                                    ; 7. byte - hi part offset of prev. MCB
                                    ;
                                    ;***************************************************************************
                                    ;	M O D I F I C A T I O N   H I S T O R Y
                                    ;
                                    ;
                                    ;       rev.      date      who  	why
                                    ;	----	----------  ---		------------------------------------
                                    ;	0.01	2003.08.03  VFX		Creation
                                    ;
                                    ;***************************************************************************
                                    ;Hardware
                                    ;***************************************************************************
                                    ;*
                                    ;*	SYSCLK: f=16.000 MHz (T= 62.5 ns)
                                    ;*
                                    ;***************************************************************************
                                    
                                    .equ	MCB_Type  = 0
                                    .equ	MCB_Proc  = 1
                                    .equ	MCB_LenL  = 2
                                    .equ	MCB_LenH  = 4
                                    .equ	MCB_PrevL = 5
                                    .equ	MCB_PrevH = 7
                                    .equ	MCB_Size  = 8
                                    
                                    
                                    .equ	MCBLast  = 7
                                    .equ	MCBFirst = 6
                                    .equ	MCBUsed  = 5
                                    .equ	ProcMask = 0x0F
                                    .equ	NonProcMask = 0xF0
                                    
                                    
                                    .equ	MMAP0 = 0x0000
                                    .equ	MMAP1 = 0x4000
                                    .equ	MMAP2 = 0x8000
                                    .equ	MMAP3 = 0xC000
                                    
                                    
                                    .equ	MaxMemoryLW = 0x0000
                                    .equ	MaxMemoryHW = 0x0002	;max memory 0x00020000 == 128kb
                                    
                                    ;
                                    ;**************************************************************************
                                    ;* Hardware Def.
                                    ;
                                    ;***************************************************************************
                                    ;**** VARIABLES
                                    .DSEG
                                    
                                    
                                    LargeMCB:	.byte	3	;Egybefuggo nagy blokkok >4kb
                                    SmallMCB:	.byte	3	;kicsi blokkok <4kb kezdopozicioja
                                    
                                    
                                    
                                    ;***************************************************************************
                                    .ESEG
                                    
                                    
                                    ;***************************************************************************
                                    ;**** CODE SEG
                                    ;***************************************************************************
                                    .CSEG
                                    
                                    ExtSRAMTest:
                                    		ldi	R20,SRAMBASE		;External SRAM Base Address
                                    		ldi	R18,8			;8x16k page = 128k
                                    		ldi	R21,0x5A		;test byte
                                    SRT0:		sts	ADR_EXHH,R20		;Upper memory to SRAM Banks
                                    		ldi	ZL,0
                                    		ldi	ZH,192			;Z point to upper memory
                                    		ldi	XL,low(16384)
                                    		ldi	XH,high(16384)		;Count of test byte
                                    
                                    srt1:		st	Z+,R21
                                    		sbiw	XL,1
                                    		brne	srt1			;fill bank
                                    		inc	R20
                                    		dec	R18
                                    		brne	SRT0
                                    
                                    
                                    
                                    		ldi	R20,SRAMBASE
                                    		ldi	R18,8
                                    		ldi	R21,0x5A		;test byte
                                    SRT2:		sts	ADR_EXHH,R20
                                    		ldi	ZL,0
                                    		ldi	ZH,192			;Z point to upper memory
                                    		ldi	XL,low(16384)
                                    		ldi	XH,high(16384)		;Count of test byte
                                    
                                    srt3:		ld	R3,Z+
                                    		cp	R21,R3
                                    		brne	SRAMERR
                                    		sbiw	XL,1
                                    		brne	srt3			;check bank
                                    		inc	R20
                                    		dec	R18
                                    		brne	srt2
                                    
                                    		clc
                                    		ret
                                    
                                    SRAMERR:	sec
                                    		ret
                                    
                                    ;******************************************************
                                    ; Convert Phisycal address to Logical Address
                                    ; In:  R18:R17:R16 Phisycal address
                                    ; Out  R18 - page,
                                    ;      R17:R16 - offset address (must add MMAP1,2,3)
                                    ;
                                    MmTranslatePhysicalAddress:
                                    		push	R17
                                    		rol	R17
                                    		rol	R18
                                    		rol	R17
                                    		rol	R18
                                    		pop	R17
                                    		andi	R17,0b00111111
                                    		ret
                                    
                                    
                                    ;******************************************************
                                    ; Set Page at R18:R16
                                    ; In:  R18:R17:R16 Phisycal address
                                    ; Out  R18 - page+1,
                                    ;      R17:R16 - offset address on MMAP2
                                    ;      Z - mapped address on MMAP2
                                    ;
                                    MmSetPage:
                                    		rcall	MmTranslatePhysicalAddress
                                    MmSetPageMap:
                                    		ori	R17,high(MMAP2)
                                    		sts	ADR_EXHL,R18
                                    		inc	R18
                                    		sts	ADR_EXHH,R18		;2 page -> no page border fault
                                    		movw	ZL,R16			;Z - offset at first page
                                    		RET
                                    
                                    
                                    
                                    
                                    ;******************************************************
                                    ; Initialize Memory & setup MCBs
                                    ;
                                    Mem_Init:
                                    		ldi	R16,S1D_DISPLAY_HEIGHT
                                    		ldi	R17,S1D_DISPLAY_SCANLINE_BYTES
                                    		mul	R16,R17
                                    		inc	R1			;skip Video RAM + 256 byte
                                    		clr	R2
                                    
                                    		sts	LargeMCB+0,R0
                                    		sts	LargeMCB+1,R1
                                    		sts	LargeMCB+2,R2		;First MCB
                                    		movw	R16,R0
                                    		mov	R18,R2
                                    		rcall	MmSetPage
                                    
                                    		ldi	R16,(1<= old delta
                                    		
                                    		movw	R12,R16
                                    		mov	R14,R18		;delta
                                    		movw	R8,R0
                                    		mov	R10,R2		;best pointer
                                    		rjmp	MMVanMeg
                                    
                                    MMTeljesenJo:
                                    		movw	R8,R0
                                    		mov	R10,R2		;pointer
                                    		clr	R12
                                    		clr	R13
                                    		clr	R14		;delta=0
                                    		rjmp	MMLastInChain
                                    
                                    
                                    MMVanMeg:
                                    		ldd	R16,Z+MCB_Type
                                    		sbrc	R16,MCBLast
                                    		 rjmp	MMLastInChain
                                    
                                    		ldd	R18,Z+MCB_LenH
                                    		ldd	R17,Z+MCB_LenL+1
                                    		ldd	R16,Z+MCB_LenL+0
                                    		add	R16,R21
                                    		adc	R17,R15
                                    		adc	R18,R15
                                    		add	R0,R16
                                    		adc	R1,R17
                                    		adc	R2,R18
                                    		rjmp	MmNextMCB01
                                    
                                    MMLastInChain:
                                    		mov	R0,R8
                                    		or	R0,R9
                                    		or	R0,R10
                                    		brne	mmMoreM00
                                    		rjmp	mmNoMoreMemory
                                    mmMoreM00:
                                    					;Memory block Allocation/sharing
                                    					;Alloc = delta < 40 byte (32+8)
                                    					;share = delta => 40 byte
                                    		ldi	R16,40
                                    		clr	R17
                                    		cp	R12,R16
                                    		cpc	R13,R17
                                    		cpc	R14,R17
                                    		brsh	MMShare
                                    
                                    mmAllocAll:	
                                    		movw	R0,R8
                                    		mov	R2,R10
                                    		movw	R16,R8
                                    		mov	R18,R10
                                    		rcall	MmSetPage
                                    
                                    		ldd	R16,Z+MCB_Type		;set MCBUsed & Process
                                    		ori	R16,(1< Proc
                                    
                                    mmMakeFree:
                                    		ldd	R16,Z+MCB_Type
                                    		cbr	R16,(1<
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language