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CHEAP ANALOG DIGITAL COMPARATOR (AVR 400)

                                    ;**** A P P L I C A T I O N   N O T E   A V R 4 0 0 ************************
                                    ;*
                                    ;* Title:		Low Cost A/D Converter 
                                    ;* Version:		1.0
                                    ;* Last updated:	97.07.18
                                    ;* Target:		AT90Sxxxx (All AVR Devices)
                                    ;*
                                    ;* Support E-mail:	avr@atmel.com
                                    ;*
                                    ;* Code Size		:37 words
                                    ;* Low Register Usage	:0
                                    ;* High Register Usage	:2
                                    ;* Status Flag Usage 	:1 (t flag)
                                    ;* Interrupt usage	:Timer/Counter0 overflow interrupt,
                                    ;*			 Analog comparator interrupt
                                    ;*
                                    ;* DESCRIPTION
                                    ;*
                                    ;* This application note shows how you can make a A/D converter using a AVR 
                                    ;* device, one external resistor and one external capacitor. This solution 
                                    ;* uses the Timer/Counter0 overflow interrupt in addition to the Analog 
                                    ;* comparator interrupt. The usage of interrupts free's the MCU while
                                    ;* conversion is taking place.
                                    ;*
                                    ;* To minimize the usage of external components, this A/D converter uses
                                    ;* the charging of a capacitor (controlled by port D pin 2)through a 
                                    ;* resistor while converting.
                                    ;* The voltage across the capacitor will follow an exponential curve of
                                    ;* voltage versus time. By constricting the voltage range of 
                                    ;* the converter to 2/5Vdd, the exponential curve is a good approximation
                                    ;* of a straight line. This makes it possible to simply measure the time
                                    ;* it takes before the voltage across the capacitor equals the voltage which
                                    ;* is to be converted. To do this we use the analog comparator. The 
                                    ;* comparator will give an interrupt when the voltage across the capacitor
                                    ;* rises above the measurement voltage. The output is divided into 64
                                    ;* different levels.
                                    ;*
                                    ;* To ensure correct timing the time constant of the RC-network must 
                                    ;* satisfie   512*(1/f)=-R*C*ln(1-2/5).
                                    ;* For the A/D converter to operate properly, the capacitor must be  
                                    ;* completly discharged between each conversion. This is done by allowing
                                    ;* the discharging to take a minimum of 200us.
                                    ;*  
                                    ;* 
                                    ;* *** Initialization
                                    ;*
                                    ;*  1. Call convert_init
                                    ;*  2. Enable global interrupts (with sei)
                                    ;* 
                                    ;* *** A/D conversion
                                    ;*
                                    ;*  1. Call AD_convert
                                    ;*  2. Wait for conversion complete (t to be set) (less than 521 cycles)
                                    ;*  3. Read data from result
                                    ;**************************************************************************
                                    
                                    
                                    .include "1200def.inc"
                                    
                                    ;***** Constants
                                    
                                    .equ	preset=192			;T/C0 Preset constant (256-64)	
                                    
                                    ;***** A/D converter Global Registers
                                    
                                    .def	result=r16			;Result and intermediate data
                                    .def	temp=r17			;Scratch register
                                    
                                    
                                    
                                    
                                    ;**************************************************************************
                                    ;*
                                    ;*  	PROGRAM START - EXECUTION STARTS HERE
                                    ;*
                                    ;**************************************************************************
                                    	.cseg
                                    
                                    
                                    	.org $0000
                                    	rjmp RESET      ;Reset handle
                                    	.org OVF0addr
                                    	rjmp ANA_COMP   ;Timer0 overflow handle
                                    	.org ACIaddr
                                    	rjmp ANA_COMP   ;Analog comparator handle
                                    
                                    
                                    
                                    ;**************************************************************************
                                    ;*
                                    ;* ANA_COMP - Analog comparator interrupt routine
                                    ;*
                                    ;*
                                    ;* DESCRIPTION
                                    ;* This routine is executed when one of two events occur:
                                    ;* 1. Timer/counter0 overflow interrupt
                                    ;* 2. Analog Comparator interrupt
                                    ;* Both events signals the end of a conversion. Timer overflow if the signal
                                    ;* is out of range, and analog comparator if it is in range.
                                    ;* The offset will be corrected, and the t'flag will be set.
                                    ;* Due to the cycles needed for interruption handling, it is necessary
                                    ;* to subtract 1 more than was added previously.
                                    ;* 
                                    ;*
                                    ;* Total numbers of words		: 7
                                    ;* Total number of cycles		: 10
                                    ;* Low register usage			: 0
                                    ;* High register usage			: 2 (result,temp)
                                    ;* Status flags				: 1 (t flag)
                                    ;*
                                    ;**************************************************************************
                                    ANA_COMP:       in      result,TCNT0    ;Load timer value
                                    
                                    	        clr     temp    	;Stop timer0
                                    		out     TCCR0,temp         
                                    
                                    		subi    result,preset+1 ;Rescale A/D output
                                    
                                    		cbi     PORTD,PD2       ;Start discharge
                                    		set			;Set conversion complete flag
                                    		
                                    		reti                    ;Return from interrupt
                                    
                                    
                                    ;**************************************************************************
                                    ;*
                                    ;* convert_init - Subroutine for A/D converter initialization
                                    ;*
                                    ;*
                                    ;* DESCRIPTION
                                    ;* This routine initializes the A/D converter. It sets the timer and the
                                    ;* analog comparator. The analog comparator interrupt is being initiated by  
                                    ;* a rising edge on AC0. To enable the A/D converter the global interurrupt
                                    ;* flag must be set (with SEI).
                                    ;*
                                    ;* The conversion complete flag (t) is cleared.
                                    ;*
                                    ;* Total number of words		: 6
                                    ;* Total number of cycles		: 10
                                    ;* Low register usage			: 0
                                    ;* High register usage			: 1 (result)
                                    ;* Status flag usage			: 0
                                    ;* 
                                    ;**************************************************************************
                                    convert_init:
                                    	        ldi     result,$0B   	;Initiate comparator
                                    		out     ACSR,result 	;and enable comparator interrupt
                                    
                                    		
                                    		ldi     result,$02      ;Enable timer interrupt
                                    		out     TIMSK,result
                                    		
                                    		sbi     PORTD,PD2       ;Set converter charge/discharge
                                    					;as output
                                    
                                    		ret			;Return from subroutine
                                    
                                    
                                    
                                    ;**************************************************************************
                                    ;*
                                    ;* AD_convert - Subroutine to start an A/D conversion
                                    ;*
                                    ;* DESCRIPTION
                                    ;* This routine starts the conversion. It loads the offset value into the
                                    ;* timer0 and starts the timer. It also starts the charging of the 
                                    ;* capacitor.
                                    ;*
                                    ;*
                                    ;* Total number of words		: 7
                                    ;* Total number of cycles		: 10
                                    ;* Low register usage			: 0
                                    ;* High register usage			: 1 (result)
                                    ;* Status flag usage			: 1 (t flag)
                                    ;*
                                    ;**************************************************************************
                                    AD_convert:
                                    		ldi     result,preset   ;Clear counter
                                    		out     TCNT0,result    ;and load offset value
                                    		
                                    		clt			;Clear conversion complete flag (t)
                                    
                                    		ldi	result,$02	;Start timer0 with prescaling f/8
                                    		out     TCCR0,result    
                                    		sbi     PORTB,PB2       ;Start charging of capacitor
                                    		
                                    
                                    		ret			;Return from subroutine
                                    
                                    
                                    ;**************************************************************************
                                    ;*
                                    ;*	Example program
                                    ;*
                                    ;* This program can be used as an example on how to set up the A/D 
                                    ;* converter properly. 
                                    ;* NOTE! To ensure proper operation, make sure the discharging period
                                    ;* of the capacitor  is longer than 200us in front of each conversion. 	
                                    ;* The results of the conversion is presented on port B.
                                    ;* To ensure proper discharging we have added a delay loop. This loop is 
                                    ;* 11 thousand cycles. This will give a 550us delay with a 20MHz oscillator
                                    ;* (11ms with a 1MHz oscillator).
                                    ;*
                                    ;**************************************************************************
                                    
                                    RESET:
                                    		rcall	convert_init	;Initialize A/D converter
                                    		sei			;Enable global interrupt
                                    		ldi	result,$ff	;set port B as output
                                    		out	DDRB,result	
                                    Delay:		clr	result		;Clear temp counter 1
                                    		ldi	temp,$f0	;Reset temp counter 2
                                    loop1:		inc	result		;Count up temp counter 1
                                    		brne	loop1		;Check if inner loop is finished
                                    		inc 	temp		;Count up temp counter 2
                                    		brne 	loop1		;Check if delay is finished
                                    
                                    		rcall	AD_convert	;Start conversion
                                    Wait:		brtc	Wait		;Wait until conversion is complete
                                    		out	PORTB,result	;Write result on port B
                                    
                                    		rjmp	Delay		;Repeat conversion
                                    
                                    
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language