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CIRCULAR REDUNDANCY CHECK (AVR 236)

                                    ;**** A P P L I C A T I O N   N O T E   A V R 236 ************************
                                    ;* 
                                    ;* Title:		CRC check of program memory
                                    ;* Version:		1.3 
                                    ;* Last updated:	11.11.2004
                                    ;* Target:		AT90Sxxx, ATtinyxxx, ATmegaxxx 
                                    ;*				(All AVR Devices with LPM instr, not AT90S1200)
                                    ;*
                                    ;* Support E-mail:	avr@atmel.com
                                    ;*
                                    ;* NOTE: Always check out Atmels web site, www.atmel.com for the latest and updated 
                                    ;* version of the software.
                                    ;*
                                    ;* DESCRIPTION
                                    ;* This application note describes how to perform CRC computation 
                                    ;* of code memory contents using a simple algoritm. 
                                    ;* To generate CRC checksum load the register "status" with 00 and call the routine 
                                    ;* "crc_gen". The resulting checksum is placed in the registers
                                    ;* byte_2(low byte) and byte_3(high byte).
                                    ;*
                                    ;* To check the CRC checksum load the register "status" with FF and call the routine 
                                    ;* "crc_gen". The resulting checksum is placed in the registers
                                    ;* byte_2(low byte) and byte_3(high byte). If the checksum is 00 the program code is
                                    ;* correct, if the checksum is non-zero an error has been introduced in the program code
                                    ;**************************************************************************
                                    
                                    
                                    .include "8515def.inc"
                                    
                                    ;***** Constants
                                    
                                    .equ		LAST_PROG_ADDR	= 0x1FFF	; Last program memory address(byte address)
                                    .equ		CR	= 0x8005	; CRC divisor value
                                    
                                    ;**************************************************************************
                                    ;*
                                    ;*      PROGRAM START - EXECUTION STARTS HERE
                                    ;*
                                    ;**************************************************************************
                                    
                                    ;        .cseg
                                    
                                    .org $0000
                                    	rjmp RESET      ;Reset handle
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "crc_gen" - Generation and checking of CRC checksum
                                    ;*
                                    ;* This subroutine generates the checksum for the program code.
                                    ;* 32 bits are loaded into 4 register, the upper 16 bits are XORed
                                    ;* with the divisor value each time a 1 is shifted into the carry flag 
                                    ;* from the MSB.
                                    ;*
                                    ;* If the status byte is 0x00,the routine will generate new checksum:
                                    ;* After the computing the code 16 zeros are
                                    ;* appended to the code and the checksum is calculated. 
                                    ;* 
                                    ;* If the status byte is different from 0X00, the routine will check if the current checksum is valid.
                                    ;* After the computing the code the original checksum are
                                    ;* appended to the code and calculated. The result is zero if no errors occurs
                                    ;* The result is placed in registers byte_2 and byte_3
                                    ;*  
                                    ;* Number of words	:44 + return
                                    ;* Number of cycles	:program memory size(word) * 175(depending on memory contens)
                                    ;* Low registers used	:6 (byte_0,byte_1,byte_2,byte_3)
                                    ;* High registers used  :7 (sizel,sizeh,crdivl,crdivh,count,status,zl,zh)	
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	byte_0	= r0		; Lower byte of lower word
                                    .def	byte_1	= r1		; Upper byte of lower word
                                    .def	byte_2	= r2		; Lower byte of upper word
                                    .def	byte_3	= r3		; Upper byte of upper word
                                    .def	crc		= r4		; CRC checksum low byte
                                    .def	crch		= r5		; CRC checksum high byte
                                    .def	sizel 	= r17	; Program code size register
                                    .def	sizeh 	= r18
                                    .def	crdivl	= r19	; CRC divisor register
                                    .def	crdivh	= r20
                                    .def count	= r21	; Bit counter 
                                    .def	status	= r22	; Status byte: generate(0) or check(1)
                                    
                                    crc_gen:
                                    	ldi 	sizel,low(LAST_PROG_ADDR) 	;Load last program memory address
                                    	ldi 	sizeh,high(LAST_PROG_ADDR)	
                                    	clr 	zl			;Clear Z pointer
                                    	clr 	zh				
                                    	ldi 	crdivh,high(CR);Load divisor value
                                    	ldi	crdivl,low(CR)
                                    	lpm				;Load first memory location
                                    	mov	byte_3,byte_0	;Move to highest byte
                                    	adiw	zl,0x01		;Increment Z pointer
                                    	lpm				;Load second memory location
                                    	mov	byte_2,byte_0		
                                    
                                    next_byte:
                                    	cp	zl,sizel		;Loop starts here
                                    	cpc	zh,sizeh		;Check for end of code
                                    	brge	end			;Jump if end of code
                                    	adiw	zl,0x01			
                                    	lpm				;Load high byte
                                    	mov	byte_1,byte_0	;Move to upper byte
                                    	adiw	zl,0x01		;Increment Z pointer
                                    	lpm				;Load program memory location
                                    	rcall 	rot_word	;Call the rotate routine
                                    	rjmp	next_byte
                                    
                                    end:	
                                    	;ret	;uncomment this line if checksum is stored in last flash memory address.
                                    	ldi	count,0x11		
                                    	cpi	status,0x00		
                                    	brne	check
                                    	clr	byte_0		;Append 16 bits(0x0000) to
                                    	clr	byte_1		;the end of the code for CRC generation
                                    	rjmp	gen	
                                    check:	
                                    	mov	byte_0,crc		;Append the original checksum to
                                    	mov	byte_1,crch    	;the end of the code for CRC checking
                                    gen:	
                                    	rcall	rot_word	;Call the rotate routine
                                    	mov	crc,byte_2		
                                    	mov	crch,byte_3
                                    	ret				;Return to main prog
                                    	
                                    rot_word:
                                    	ldi	count,0x11
                                    rot_loop:
                                    	dec 	count		;Decrement bit counter
                                    	breq	stop			;Break if bit counter = 0
                                    	lsl	byte_0		;Shift zero into lowest bit
                                    	rol	byte_1		;Shift in carry from previous byte
                                    	rol	byte_2		;Preceede shift
                                    	rol	byte_3			
                                    	brcc	rot_loop		;Loop if MSB = 0			
                                    	eor 	byte_2,crdivl
                                    	eor 	byte_3,crdivh	;XOR high word if MSB = 1
                                    	rjmp	rot_loop
                                    stop:	
                                    	ret
                                    
                                    ;***************************************************************************
                                    ;* 
                                    ;* EERead_seq
                                    ;*
                                    ;* This routine reads the 
                                    ;* EEPROM into the global register variable "temp".
                                    ;*
                                    ;* Number of words	:4+ return
                                    ;* Number of cycles	:8 + return 
                                    ;* High Registers used	:4 (temp,eeadr,eeadrh,eedata)
                                    ;*
                                    ;***************************************************************************
                                    
                                    .def	temp		= r16 
                                    .def	eeadr	= r23
                                    .def	eeadrh	= r24
                                    .def	eedata	= r25
                                    
                                    ;***** Code
                                    
                                    eeread:
                                    	out	EEARH,eeadrh	;output address high byte
                                    	out	EEARL,eeadr	;output address low byte
                                    	sbi	EECR,EERE		;set EEPROM Read strobe
                                    	in	eedata,EEDR	;get data
                                    	ret
                                    
                                    ;***************************************************************************
                                    ;* 
                                    ;* EEWrite
                                    ;*
                                    ;* This subroutine waits until the EEPROM is ready to be programmed, then
                                    ;* programs the EEPROM with register variable "EEdwr" at address "EEawr"
                                    ;*
                                    ;* Number of words	:7 + return
                                    ;* Number of cycles	:13 + return (if EEPROM is ready)
                                    ;* Low Registers used	:None
                                    ;* High Registers used:	;4 (temp,eeadr,eeadr,eedata)
                                    ;*
                                    ;***************************************************************************
                                    
                                    .def	temp		= r16 
                                    .def	eeadr	= r23
                                    .def	eeadrh	= r24
                                    .def	eedata	= r25
                                    
                                    eewrite:
                                    	sbic	EECR,EEWE	;If EEWE not clear
                                    	rjmp	EEWrite		;    Wait more
                                    	out	EEARH,eeadrh	;Output address high byte
                                    	out	EEARL,eeadr	;Output address low byte
                                    	out	EEDR,eedata	;Output data
                                    	sbi	EECR,EEMWE
                                    	sbi	EECR,EEWE		;Set EEPROM Write strobe
                                    	ret
                                    
                                    ;************************************************************************
                                    ;*
                                    ;*  Start Of Main Program
                                    ;*
                                    .cseg
                                    .def	crc		= r4		;Low byte of checksum to be returned
                                    .def	crch		= r5		;High byte of checksum to be returned
                                    .def	temp		= r16  
                                    .def	status	= r22	;Status byte: generate(0) or check(1)
                                    .def	eeadr	= r23
                                    .def	eeadrh	= r24
                                    .def	eedata	= r25
                                    
                                    RESET:	
                                    	ldi	r16,high(RAMEND)	;Initialize stack pointer	
                                    	out	SPH,r16			;High byte only required if 
                                    	ldi	r16,low(RAMEND)	;RAM is bigger than 256 Bytes
                                    	out	SPL,r16
                                    
                                    	ldi 	temp,0xff	
                                    	out 	DDRB,temp		;Set PORTB as output
                                    	out 	PORTB,temp	;Write 0xFF to PORTB
                                    	clr 	status		;Clear status register, prepare for CRC generation
                                    	rcall 	crc_gen
                                    	
                                    	ldi 	eeadr,0x01	;Set address low byte for EEPROM write
                                    	ldi 	eeadrh,0x00	;Set address high byte for EEPROM write
                                    	mov 	eedata,crc	;Set CRC low byte in EEPROM data
                                    	rcall	eewrite		;Write EEPROM
                                    
                                    	ldi 	eeadr,0x02	;Set address low byte for EEPROM write
                                    	ldi 	eeadrh,0x00	;Set address high byte for EEPROM write
                                    	mov 	eedata,crch	;Set CRC high byte in EEPROM data
                                    	rcall	eewrite		;Write EEPROM
                                    
                                    	out 	PORTB,crc	;Output CRC low value to PORTB
                                    	
                                    mainloop:
                                    	sbic	EECR,EEWE	;If EEWE not clear
                                    	rjmp	mainloop	;    Wait more
                                    
                                    ;********** Insert program code here *************
                                    
                                    	ldi 	eeadr,0x01	;Set address low byte for EEPROM read
                                    	ldi 	eeadrh,0x00	;Set address high byte for EEPROM read
                                    	rcall	eeread		;Read EEPROM
                                    	mov 	crc,eedata	;Read CRC low byte from EEPROM
                                    
                                    	ldi 	eeadr,0x02	;Set address low byte for EEPROM read
                                    	ldi 	eeadrh,0x00	;Set address high byte for EEPROM read
                                    	rcall	eeread		;Read EEPROM
                                    	mov 	crch,eedata	;Read CRC low byte from EEPROM
                                    
                                    	ser	status		;Set status register, prepare for CRC checking
                                    	rcall 	crc_gen
                                    
                                    loop:	
                                    	out	PORTB,crc	;Output CRC low value to PORTB
                                    	rjmp loop
                                    
                                    .exit
                                    
                                    
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language