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AT KEYBOARD PROGRAM 128

                                    Below is some assembly code I wrote for the mega128 last fall. It worked but has not been tested extensively. I did a look-up
                                    table to give me a ASCII character for the corresponding keyboard scan code.
                                    
                                    
                                    ; Date:               9/26/03 
                                    ; By:               Stephen L. Nuttall 
                                    ; Hardware platform;   STK500/STK501 
                                    ; Software platform:   Atmel Studio 4.07 
                                    ; File location:      C:\My Documents\AVR Projects\keyboard4a\keyboard4a.asm 
                                    ; Clock frequency:      3.6864MHz (via STK500 onboard oscillator) 
                                    ; 
                                    ; 
                                    ; The purpose of this project is to: 
                                    ;    1. Read a keyboard scan code using the keyboard SCL and SDA lines 
                                    ;   2. Determine if the scan code is 0xAA in which case it will transmit 
                                    ;       "Basic Assurance Test complete" via USART0 
                                    ;   3. Determine if the scan code is 0xF0, if it is not it will look up and 
                                    ;       transmit the equivalent ASCII code for that key (in other words, 
                                    ;       if the key is held down it will keep transmitting that ASCII character). 
                                    ;       If it is 0xF0 then it will transmit the word "Break" and then wait for 
                                    ;       the next scan code 
                                    ;   4. Only the alphabet and number keys are decoded in this code. The Ctrl, Alt, 
                                    ;      Shift, Enter, Function, etc. keys are not decoded. Hitting one of those keys 
                                    ;      will result in a capital letter or a "?" being sent via the USART0. You can 
                                    ;      look at the table at the end of the code and get an idea of what I mean. 
                                    ; 
                                    ; This project will use code from previous projects as well as code 
                                    ; from keyboard5.asm, keyboard5a.asm and keyboard5b.asm. 
                                    ; 
                                    .nolist 
                                    .include "m128def.inc" 
                                    .list 
                                    ; 
                                    .def   temp      = R16 
                                    .def   bitcntr      = R17 
                                    .def    keydata      = R18 
                                    .def    temphi      = R19 
                                    .def   templo      = R20 
                                    .def   flags      = R21 
                                    .def    parity      = R22 
                                    ; 
                                    .org   0x0000 
                                       jmp    RESET             ; Reset Handler 
                                    
                                    .org   0x0046 
                                    
                                    RESET:                     ; Main program start 
                                       ldi      temp, high(RAMEND)   ; Stack pointer = top of internal SRAM 
                                       out    SPH,temp  
                                       ldi    temp, low(RAMEND)  
                                       out    SPL,temp  
                                       ser      temp            ; PortB = 
                                       out      DDRB,temp         ;     all outputs 
                                       out      PORTB,temp         ; PortB LED's = off 
                                       ldi      temp,0b11111100      ; PortD0 and PortD1 = inputs, all 
                                       out      DDRD,temp         ;  other pins = output 
                                       com      temp            ; temp now becomes 0b00000011 
                                       out      PORTD,temp         ; PortD0 and PortD1 have pullups 
                                                            ;  enabled, remaining pins output 0's 
                                    
                                       ldi      temphi,0x00         ; setup BAUD rate for 9600 @ 3.6864MHz 
                                       ldi      templo,0x17 
                                       sts      UBRR0H,temphi      ; "sts" is used because UBRR0H is not within reach 
                                                                   ; of "out" 
                                       out      UBRR0L,templo      ; UBRR0L is within reach of "out" 
                                    
                                    ;*********************************************************************************** 
                                    ; USART 
                                    ; Frame format = 1 start bit, 8 data bits, no parity bit, 1 stop bit (8,N,1) 
                                    ; 
                                    ; Registers UCSR0B and UCSR0C are already setup for this Frame format at RESET. 
                                    ; 
                                    ; No programming action is required for the above registers...if any settings need 
                                    ; to be changed I need to remember that UCSR0C cannot be accessed via the OUT 
                                    ; instruction, use STS instead. 
                                    ; 
                                    ;*********************************************************************************** 
                                    ; 
                                    init: 
                                       clr      bitcntr            ; initialize appropriate registers 
                                       clr      keydata 
                                       clr      parity 
                                       clr      flags 
                                    
                                    main: 
                                       call   sclhi            ; make sure SCL is high to start off 
                                       call   scllo            ; look for SCL going low 
                                       inc      bitcntr    
                                       cpi      bitcntr,0x01      ; is this a Start bit? 
                                       breq   startbit         ; yes, go check Start bit 
                                       cpi      bitcntr,0x0A      ; is this a Data bit? 
                                       brlt   databit            ; yes, go get Data bit 
                                       breq   paritybit         ; no, go get and calculate parity 
                                       cpi      bitcntr,0x0B      ; is this a Stop bit 
                                       breq   stopbit            ; yes, go check Stop bit 
                                    
                                    startbit: 
                                       sbic   PIND,PD1         ; Start bit = 0? 
                                       rjmp   starterr         ; no...go send error message 
                                       rjmp   main            ; yes..go look for data bits 
                                    
                                    databit: 
                                       bclr   0               ; pre-clear Carry flag 
                                       sbic   PIND,PD1         ; SDA = 0? 
                                       bset   0               ; no, then set Carry flag 
                                       brbc   0,rotate         ; now check status of Carry flag for parity chk 
                                       in      flags,SREG         ; save 
                                       push   flags            ;  status register 
                                       inc      parity            ; for parity check later 
                                       pop      flags            ; restore 
                                       out      SREG,flags         ;  status register 
                                    rotate: 
                                       ror      keydata            ; rotate contents of Carry flag into keydata 
                                       rjmp   main            ; go get another bit 
                                    ; 
                                    ; Parity checking..... 
                                    ; this routine is based on Odd Parity; meaning if there are an even number of 1's 
                                    ; in the data byte the Parity bit will be 1 so that an odd number of 1's now exist, 
                                    ; if there are already an odd number of 1's then the Parity bit will be 0. 
                                    ; 
                                    ; I will keep track of Parity by incrementing the parity register once for every 1 
                                    ; that is received on the data line. If there are an odd number of 1's the lsb of 
                                    ; parity register will always be 1 
                                    ; 
                                    ; Therefore, if the lsb of the parity register = 1 (odd number of 1's) then the 
                                    ; Parity bit should be 0 (there were an odd number of 1's already. This condition 
                                    ; can be checked by exclusive ORing those 2 bits. As long as they are opposite 
                                    ; the parity checks out good. 
                                    ; 
                                    paritybit: 
                                       in      flags,PIND         ; SDA = PD1 
                                       ror      flags            ; rotate SDA into bit 0 position 
                                       andi   flags,0x01         ; clear all but bit 0 position 
                                       andi   parity,0x01         ; again, clear all but bit 0 
                                       eor      flags,parity      ; exclusive-or to find out if lsb's of flags 
                                                            ;  and parity the same 
                                       breq   parerr            ; report error if they are the same 
                                       rjmp   main            ; return and get stop bit now 
                                    
                                    stopbit: 
                                       sbis   PIND,PD1         ; SDA = 1? 
                                       rjmp   stoperr            ; no, go report error 
                                       cpi      keydata,0xAA      ; BAT message from keyboard? 
                                       brne   chkforbrkcode      ; no, check for next code of interest 
                                       ldi      ZH,high(2*batmsg)   ; pre-load BAT message address 
                                       ldi      ZL,low(2*batmsg) 
                                       call   sendmsg            ; go send message 
                                       rjmp   init            ; go look for another key press 
                                    
                                    chkforbrkcode: 
                                       cpi      keydata,0xF0      ; Break code (0xF0):? 
                                       brne   sendkeychar         ; no, go send ASCII key code 
                                       ldi      ZH,high(2*brkmsg)   ; yes, now pre-load Break message address 
                                       ldi      ZL,low(2*brkmsg) 
                                       call   sendmsg            ; go send message 
                                       rjmp   init            ; look for another keypress 
                                    
                                    
                                    starterr: 
                                       ldi      ZH,high(2*sterrmsg)   ; load high part of message address in ZH 
                                       ldi      ZL,low(2*sterrmsg)   ; load low part of message address in ZL 
                                       call   senderrmsg 
                                    
                                    parerr: 
                                       ldi      ZH,high(2*parerrmsg); load high part of message address in ZH 
                                       ldi      ZL,low(2*parerrmsg)   ; load low part of message address in ZL 
                                       call   senderrmsg 
                                    
                                    stoperr: 
                                       ldi      ZH,high(2*sperrmsg)   ; load high part of message address in ZH 
                                       ldi      ZL,low(2*sperrmsg)   ; load low part of message address in ZL 
                                       call   senderrmsg 
                                    
                                    ;********* Subroutines ************** 
                                    
                                    scllo: 
                                       sbic   PIND,PD0         ; PD0(SCL) = 0?    
                                       rjmp   scllo            ; no...continue checking SCL 
                                       ret                     ; yes...return main program 
                                    
                                    sclhi: 
                                       sbis   PIND,PD0         ; PD0(SCL) = 1? 
                                       rjmp   sclhi            ; no...continue checking SCL 
                                       ret                     ; yes..return to main program 
                                    
                                    getsda: 
                                       bclr   0               ; pre-clear the Carry flag 
                                       sbic   PIND,PD1         ; check state of SDA 
                                       bset   0               ;  if SDA = 1, set Carry flag 
                                       ret                     ;  if SDA = 0. Carry flag is already cleared 
                                    
                                    ;****************************************************************************** 
                                    senderrmsg: 
                                    ; the calling program will have to load ZH and ZL with the appropriate message 
                                    ; address 
                                    
                                       sbi      UCSR0B,TXEN0      ; enable transmitter, TXEN = 1 
                                    getmsg: 
                                       lpm      R0,Z+            ; retrieve character from program memory 
                                       tst      R0               ; is it the last character? 
                                       breq      loop         ; yes..then loop forever 
                                       out      UDR0,R0            ; no...transmit character          
                                       call   chkxmitend         ; wait for transmit to finish 
                                       rjmp   getmsg            ; get next character 
                                    
                                    loop: 
                                       cbi      UCSR0B,TXEN0      ; disable transmitter 
                                       rjmp   loop            ; program stops here when error occurs, user 
                                                            ;  will have to reset the STK500 and try again 
                                    
                                    ;****************************************************************************** 
                                    sendmsg: 
                                    ; the calling program will have to load ZH and ZL with the appropriate message 
                                    ; address 
                                    
                                       sbi      UCSR0B,TXEN0      ; enable transmitter, TXEN = 1 
                                    getmsg1: 
                                       lpm      R0,Z+            ; retrieve character from program memory 
                                       tst      R0               ; is it the last character? 
                                       breq   continue         ; yes..then loop forever 
                                       out      UDR0,R0            ; no...transmit character          
                                       call   chkxmitend         ; wait for transmit to finish 
                                       rjmp   getmsg1            ; get next character 
                                    continue: 
                                       cbi      UCSR0B,TXEN0      ; disable transmitter 
                                       ret 
                                    
                                    ;****************************************************************************** 
                                    sendkeychar: 
                                    
                                       sbi      UCSR0B,TXEN0      ; enable transmitter, TXEN = 1 
                                    
                                       ldi      ZH,high(2*ascii)   ; load high part of key character address in ZH 
                                       ldi      ZL,low(2*ascii)      ; load low part of key character address in ZL 
                                       add      ZL,keydata         ; add keydata offset to ZL register 
                                       brcc   getchar            ; if no carry, load key character in R0 
                                       inc      ZH               ; if there is a carry, increment ZH register 
                                    
                                    getchar: 
                                       lpm                     ; load appropriate key character into R0 
                                       out      UDR0,R0            ; no...transmit character 
                                       call   chkxmitend         ; wait for transmit to finish 
                                       cbi      UCSR0B,TXEN0      ; disable transmitter 
                                       ret 
                                    
                                    ;****************************************************************************** 
                                    
                                    chkxmitend: 
                                       sbis   UCSR0A,UDRE0      ; data register empty flag = 1 
                                       rjmp   chkxmitend         ; no...keep checking 
                                       ret                     ; yes..continue with program 
                                    
                                    
                                    ;************* MESSAGES ****************************************************** 
                                    
                                    batmsg: 
                                       .db   "  Basic Assurance Test complete  ",0 
                                        
                                    brkmsg: 
                                       .db   "   Break   ",0 
                                    
                                    
                                    ; ************* ERROR MESSAGES ************************************************ 
                                    
                                    sterrmsg: 
                                       .db   "Start Bit Error",0 
                                        
                                    parerrmsg: 
                                       .db   "Parity Bit Error" 
                                       .db   0,0 
                                    
                                    sperrmsg: 
                                       .db   "Stop Bit Error" 
                                       .db   0,0 
                                    
                                    ; ************ KEY CHARACTERS ************************************************ 
                                    
                                    ascii: 
                                    ; 0x00 - 0x0F 
                                    .db   '?','F','?','F','F','F','F','F','?','F','F','F','F','T','`','?' 
                                    
                                    ; 0x10 - 0x1F 
                                    .db   '?','L','L','?','L','q','1','?','?','?','z','s','a','w','2','?' 
                                    
                                    ; 0x20 - 0x2F 
                                    .db   '?','c','x','d','e','4','3','?','?','S','v','f','t','r','5','?' 
                                    
                                    ; 0x30 - 0x3F 
                                    .db   '?','n','b','h','g','y','6','?','?','?','m','j','u','7','8','?' 
                                    
                                    ; 0x40 - 0x4F 
                                    .db   '?',',','k','i','o','0','9','?','?','.','/','l',';','p','-','?' 
                                    
                                    ; 0x50 - 0x5F 
                                    .db   '?','?',''','?','[','=','?','?','C','R','E',']','?','\','?','?' 
                                    
                                    ; 0x60 - 0x6F 
                                    .db   '?','?','?','?','?','?','B','?','?','1','?','4','7','?','?','?' 
                                    
                                    ; 0x70 - 0x7F 
                                    .db   '0','.','2','5','6','8','E','N','F','+','3','-','*','9','S','?' 
                                    
                                    ; 0x80 - 0x83 
                                    .db   '?','?','?','F' 
                                     
                                     
                                    
                                    
                                    
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language