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REAL TIME CLOCK FOR EPSON 8564

                                    ;***************************************************************************
                                    ;
                                    ; File Name		:'RTC8564.asm"
                                    ; Title			:Epson RTC8564JE Driver
                                    ; Date			:2003.04.30.	Lastmod.:[2003.04.30.]
                                    ; Version		:1.0.0
                                    ; Support telephone	:+36-70-333-4034,  Old: +36-30-9541-658 VFX
                                    ; Support fax		:
                                    ; Support Email		:info@vfx.hu
                                    ; Target MCU		:ATmaga128
                                    ;
                                    ;***************************************************************************
                                    ;	D E S C R I P T I O N
                                    ;
                                    ;  Real Time Clock Modul Driver
                                    ;
                                    ;
                                    ;***************************************************************************
                                    ;	M O D I F I C A T I O N   H I S T O R Y
                                    ;
                                    ;
                                    ;       rev.      date      who		why
                                    ;	----	----------  ---		--------------------------------------------
                                    ;	0.01	2003.04.30  VFX		Creation
                                    ;
                                    ;***************************************************************************
                                    ;
                                    ;
                                    ;
                                    ;Hardware
                                    ;***************************************************************************
                                    ;*
                                    
                                    
                                    ;**************************************************************************
                                    ;* Const Def
                                    ;
                                    
                                    .equ	RTC_SlaveAddr = 0b10100010
                                    
                                    
                                    ; RTC internal Registers
                                    ; All data address 0x02 through 05 & 0x08 through 0x0B is in BCD format
                                    .equ	RTC_Control1 = 0x00
                                    .equ	RTC_Control2 = 0x01
                                    .equ	RTC_Seconds  = 0x02
                                    .equ	RTC_Minutes  = 0x03
                                    .equ	RTC_Hours    = 0x04
                                    .equ	RTC_Days     = 0x05
                                    .equ	RTC_WeekDays = 0x06
                                    .equ	RTC_Months   = 0x07
                                    .equ	RTC_Years    = 0x08
                                    .equ	RTC_MinuteAlarm = 0x09
                                    .equ	RTC_HourAlarm   = 0x0A
                                    .equ	RTC_DayAlarm    = 0x0B
                                    .equ	RTC_WeekdayAlarm= 0x0C
                                    .equ	RTC_CLKOUT_Freq = 0x0D
                                    .equ	RTC_TimerControl= 0x0E
                                    .equ	RTC_Timer       = 0x0F
                                    
                                    
                                    ;RTC Commands
                                    ;Control Register 1
                                    .equ	RTC_StopRunning = 0b00100000
                                    .equ	RTC_ContRunning = 0b00000000
                                    
                                    ;Control Register 2
                                    .equ	RTC_AlarmIntEnable =  0b00000010
                                    .equ	RTC_AlarmIntDisable=  0b00000000
                                    
                                    ;Seconds [addr 0x02]
                                    .equ	RTC_LowBat = 0b10000000
                                    
                                    ;century [Addr 0x07]
                                    .equ	RTC_Cetury  = 0b10000000
                                    
                                    
                                    
                                    
                                    ;***************************************************************************
                                    .DSEG
                                    
                                    IO_CTR_RTC:	.byte 17		;IO buffer for RTC controll
                                    					;Time -> 00:00:00 + Line end
                                    				    	;Date -> 2000-01-01 + Line end
                                    
                                    
                                    ;*************************************************************************
                                    ;*  Text Const
                                    ;*
                                    .CSEG
                                    
                                    ;*************************************************************************
                                    ;*  Read RTC All dataa
                                    ;*
                                    RTC_ReadALL:
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			ldi	R17,16				;reads 16 byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,0				;Begining fo read
                                    			rcall	TWI_StartRead
                                    			ret
                                    
                                    ;*************************************************************************
                                    ;*  Start RTC
                                    ;*
                                    RTC_Start:
                                    			rcall	WaitToTWI
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			ldi	R16,RTC_ContRunning
                                    			st	X,R16
                                    			ldi	R17,1				;write 16 byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,0				;Begining of write
                                    			rcall	TWI_StartWrite
                                    			ret
                                    
                                    ;*************************************************************************
                                    ;*  Stop RTC
                                    ;*
                                    RTC_Stop:
                                    			rcall	WaitToTWI
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			ldi	R16,RTC_StopRunning
                                    			st	X,R16
                                    			ldi	R17,1				;write 1 byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,0				;Begining of write
                                    			rcall	TWI_StartWrite
                                    			ret
                                    
                                    ;******************************************************************
                                    ;* RTC Low Battery detector
                                    ;
                                    ; Out:
                                    ; z = 1 TWI Error
                                    ; z = 0 No error and
                                    ; 		c=1 Battery Low
                                    ; 		c=0 Battery Ok
                                    RTC_BatLow:
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			ldi	R17,1				;read 1 byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,RTC_Seconds			;Begining of read
                                    			rcall	TWI_StartRead
                                    			rcall	WaitToTWI
                                    			brcs	RTC_BatLow1
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			ld	R16,X
                                    			rol	R16				;csak a c=VL bit marad
                                    			clz
                                    			ret
                                    RTC_BatLow1:		sez					;TWI Error
                                    			ret
                                    
                                    LowBatS:	.db	"RTC Battery is Low - Check Date/Time",CR,0
                                    noRTC:		.db	"RTC not found - setup date/time manualy ",CR,0
                                    
                                    ;***************************************************************************
                                    ; RTC Get Time
                                    ;
                                    ; In:  -
                                    ; Out: var X -> IO_CTR_RTC (00:00:00+zero byte) ASCCI
                                    ;	   R4:R3:R2 - hh:mm:ss  BCD
                                    ; Used:
                                    
                                    RTC_GetTime:
                                    	       		rcall	RTC_Stop
                                    			ldi	XL,Low(IO_CTR_RTC+1)
                                    			ldi	XH,High(IO_CTR_RTC+1)
                                    			ldi	R17,3				;noumber of byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,RTC_Seconds
                                    			rcall	TWI_StartRead
                                    			rcall	RTC_Start
                                    
                                    			ldi	ZL,Low(IO_CTR_RTC+1)
                                    			ldi	ZH,High(IO_CTR_RTC+1)
                                    			ldd	R16,Z+0				;sec
                                    			andi	R16,0b01111111
                                    			mov	R2,R16
                                    			ldd	R16,Z+1				;min
                                    			andi	R16,0b01111111
                                    			mov	R3,R16
                                    			ldd	R16,Z+2				;hrs
                                    			andi	R16,0b00111111
                                    			mov	R0,R16
                                    			mov	R4,R16
                                    			rcall	BCDToASCII
                                    			std	Z+0,R1
                                    			std	Z+1,R0
                                    			ldi	R17,':'
                                    			std	Z+2,R17
                                    			mov	R0,R3
                                    			rcall	BCDToASCII
                                    			std	Z+3,R1
                                    			std	Z+4,R0
                                    			std	Z+5,R17
                                    			mov	R0,R2
                                    			rcall	BCDToASCII
                                    			std	Z+6,R1
                                    			std	Z+7,R0
                                    			clr	R16
                                    			std	Z+8,R16
                                    			movw	XL,ZL
                                    			ret
                                    
                                    ;***************************************************************************
                                    ; RTC Set Time
                                    ;
                                    ; In:  R4:R3:R2  -> hh:mm:ss  BCD
                                    ; Out:  c = 0 sucess
                                    ;	c = 1 error
                                    ; Used:
                                    ;
                                    RTC_SetTime:
                                    	       		rcall	RTC_Stop
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			rcall	WaitToTWI
                                    			st	X+,R2
                                    			st	X+,R3
                                    			st	X,R4
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                     			ldi	R17,3				;noumber of byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,RTC_Seconds
                                    			rcall	TWI_StartWrite
                                    			rcall	RTC_Start
                                    			ret
                                    
                                    ;***************************************************************************
                                    ; RTC Set Date
                                    ;
                                    ; In:	R4:R3:R2  -> yy:mm:dd  BCD
                                    ;	R5 - Century bit 0/1
                                    ; Out:  c = 0 sucess
                                    ;	c = 1 error
                                    ; Used:
                                    ;
                                    RTC_SetDate:
                                    			clr	R16
                                    			ror	R5
                                    			ror	R16
                                    			or	R3,R16
                                    	       		rcall	RTC_Stop
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			rcall	WaitToTWI
                                    			st	X+,R3
                                    			st	X,R4
                                    			sbiw	XL,1
                                     			ldi	R17,2				;noumber of byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,RTC_Months
                                    			rcall	TWI_StartWrite
                                    			rcall	WaitToTWI
                                    			ldi	XL,Low(IO_CTR_RTC)
                                    			ldi	XH,High(IO_CTR_RTC)
                                    			st	X,R2
                                     			ldi	R17,1				;noumber of byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,RTC_Days
                                    			rcall	TWI_StartWrite
                                    			rcall	RTC_Start
                                    			ret
                                    
                                    ;***************************************************************************
                                    ; RTC Get Date
                                    ;
                                    ; In:  -
                                    ; Out: var X -> IO_CTR_RTC (yyyy-mm-dd+zero byte) ASCCI
                                    ;	   R4:R3:R2 - yy-mm-dd  BCD
                                    ;	   R5 - Century bit
                                    ; Used:
                                    
                                    RTC_GetDate:
                                    	       		rcall	RTC_Stop
                                    			ldi	XL,Low(IO_CTR_RTC+1)
                                    			ldi	XH,High(IO_CTR_RTC+1)
                                    			ldi	R17,4				;noumber of byte
                                    			ldi	R18,RTC_SlaveAddr		;Slave Address
                                    			ldi	R19,RTC_Days
                                    			rcall	TWI_StartRead
                                    			rcall	RTC_Start
                                    
                                    			ldi	ZL,Low(IO_CTR_RTC+1)
                                    			ldi	ZH,High(IO_CTR_RTC+1)
                                    			ldd	R16,Z+0				;days
                                    			andi	R16,0b00111111
                                    			mov	R2,R16
                                    			ldd	R16,Z+2
                                    			mov	R5,R16
                                    			andi	R16,0b00011111
                                    			mov	R3,R16
                                    			rol	R5
                                    			clr	R5
                                    			rol	R5
                                    			tst	R5
                                    			brne	XXICentury
                                    			ldi	R16,'1'
                                    			std	Z+0,R16
                                    			ldi	R16,'9'
                                    			rjmp	CenturyOk
                                    XXICentury:
                                    			ldi	R16,'2'
                                    			std	Z+0,R16
                                    			ldi	R16,'0'
                                    CenturyOk:
                                    			std	Z+1,R16
                                    
                                    			ldd	R16,Z+3				;years
                                    			mov	R0,R16
                                    			mov	R4,R16
                                    			rcall	BCDToASCII
                                    			std	Z+2,R1
                                    			std	Z+3,R0
                                    			ldi	R17,'-'
                                    			std	Z+4,R17
                                    			mov	R0,R3
                                    			rcall	BCDToASCII
                                    			std	Z+5,R1
                                    			std	Z+6,R0
                                    			std	Z+7,R17
                                    			mov	R0,R2
                                    			rcall	BCDToASCII
                                    			std	Z+8,R1
                                    			std	Z+9,R0
                                    			clr	R16
                                    			std	Z+10,R16
                                    			movw	XL,ZL
                                    			ret
                                    
                                    
                                    
                                    
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language