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FAST MULTIPLY & DIVIDE (AVR 200b)

                                    ;**** A P P L I C A T I O N   N O T E   A V R 2 0 0 b ************************
                                    ;*
                                    ;* Title:		Multiply and Divide Routines
                                    ;* Version:		1.1
                                    ;* Last updated:	97.07.04
                                    ;* Target:		AT90Sxxxx (All AVR Devices)
                                    ;*
                                    ;* Support E-mail:	avr@atmel.com
                                    ;* 
                                    ;* DESCRIPTION
                                    ;* This Application Note lists subroutines for the following
                                    ;* Muliply/Divide applications. Routines are straight-line implementations
                                    ;* optimized for speed:
                                    ;*
                                    ;*  8 x  8 = 16 bit unsigned
                                    ;* 16 x 16 = 32 bit unsigned
                                    ;*  8 /  8 =  8 +  8 bit unsigned
                                    ;* 16 / 16 = 16 + 16 bit unsigned
                                    ;*
                                    ;***************************************************************************
                                    
                                    .include "1200def.inc"
                                    
                                    	rjmp	RESET	;reset handle
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "mpy8u" - 8x8 Bit Unsigned Multiplication
                                    ;*
                                    ;* This subroutine multiplies the two register variables mp8u and mc8u.
                                    ;* The result is placed in registers m8uH, m8uL
                                    ;*  
                                    ;* Number of words	:34 + return
                                    ;* Number of cycles	:34 + return
                                    ;* Low registers used	:None
                                    ;* High registers used  :3 (mc8u,mp8u/m8uL,m8uH)	
                                    ;*
                                    ;* Note: Result Low byte and the multiplier share the same register.
                                    ;* This causes the multiplier to be overwritten by the result.
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	mc8u	=r16		;multiplicand
                                    .def	mp8u	=r17		;multiplier
                                    .def	m8uL	=r17		;result Low byte
                                    .def	m8uH	=r18		;result High byte
                                    
                                    ;***** Code
                                    
                                    mpy8u:	clr	m8uH		;clear result High byte
                                    	lsr	mp8u		;shift multiplier
                                    	
                                    	brcc	noad80		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad80:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    
                                    	brcc	noad81		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad81:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    
                                    	brcc	noad82		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad82:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    
                                    	brcc	noad83		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad83:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    
                                    	brcc	noad84		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad84:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    
                                    	brcc	noad85		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad85:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    
                                    	brcc	noad86		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad86:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    
                                    	brcc	noad87		;if carry set
                                    	add	m8uH,mc8u	;    add multiplicand to result High byte
                                    noad87:	ror	m8uH		;shift right result High byte 
                                    	ror	m8uL		;rotate right result L byte and multiplier
                                    	
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "mpy16u" - 16x16 Bit Unsigned Multiplication
                                    ;*
                                    ;* This subroutine multiplies the two 16-bit register variables 
                                    ;* mp16uH:mp16uL and mc16uH:mc16uL.
                                    ;* The result is placed in m16u3:m16u2:m16u1:m16u0.
                                    ;*  
                                    ;* Number of words	:105 + return
                                    ;* Number of cycles	:105 + return
                                    ;* Low registers used	:None
                                    ;* High registers used  :6 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/m16u1,m16u2,
                                    ;*			    m16u3)	
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    
                                    
                                    .def	mc16uL	=r16		;multiplicand low byte
                                    .def	mc16uH	=r17		;multiplicand high byte
                                    .def	mp16uL	=r18		;multiplier low byte
                                    .def	mp16uH	=r19		;multiplier high byte
                                    .def	m16u0	=r18		;result byte 0 (LSB)
                                    .def	m16u1	=r19		;result byte 1
                                    .def	m16u2	=r20		;result byte 2
                                    .def	m16u3	=r21		;result byte 3 (MSB)
                                    
                                    ;***** Code
                                    
                                    mpy16u:	clr	m16u3		;clear 2 highest bytes of result
                                    	clr	m16u2	
                                    	lsr	mp16uH		;rotate multiplier Low
                                    	ror	mp16uL		;rotate multiplier High
                                    
                                    	brcc	noadd0		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd0:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd1		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd1:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd2		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd2:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd3		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd3:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd4		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd4:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd5		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd5:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd6		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd6:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd7		;if carry sett
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd7:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd8		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd8:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noadd9		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noadd9:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noad10		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noad10:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noad11		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noad11:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noad12		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noad12:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noad13		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noad13:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noad14		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noad14:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	brcc	noad15		;if carry set
                                    	add	m16u2,mc16uL	;    add multiplicand Low to byte 2 of res
                                    	adc	m16u3,mc16uH	;    add multiplicand high to byte 3 of res
                                    noad15:	ror	m16u3		;shift right result byte 3
                                    	ror	m16u2		;rotate right result byte 2
                                    	ror	m16u1		;rotate result byte 1 and multiplier High
                                    	ror	m16u0		;rotate result byte 0 and multiplier Low
                                    
                                    	ret
                                    
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "div8u" - 8/8 Bit Unsigned Division
                                    ;*
                                    ;* This subroutine divides the two register variables "dd8u" (dividend) and 
                                    ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in
                                    ;* "drem8u".
                                    ;*  
                                    ;* Number of words	:66 + return
                                    ;* Number of cycles	:50/58/66 (Min/Avg/Max) + return
                                    ;* Low registers used	:1 (drem8u)
                                    ;* High registers used  :2 (dres8u/dd8u,dv8u)
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	drem8u	=r15		;remainder
                                    .def	dres8u	=r16		;result
                                    .def	dd8u	=r16		;dividend
                                    .def	dv8u	=r17		;divisor
                                    
                                    ;***** Code
                                    
                                    div8u:	sub	drem8u,drem8u	;clear remainder and carry
                                    	
                                    	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_1		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_2		;else
                                    d8u_1:	sec			;    set carry to be shifted into result
                                    
                                    d8u_2:	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_3		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_4		;else
                                    d8u_3:	sec			;    set carry to be shifted into result
                                    
                                    d8u_4:	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_5		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_6		;else
                                    d8u_5:	sec			;    set carry to be shifted into result
                                    
                                    d8u_6:	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_7		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_8		;else
                                    d8u_7:	sec			;    set carry to be shifted into result
                                    
                                    d8u_8:	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_9		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_10		;else
                                    d8u_9:	sec			;    set carry to be shifted into result
                                    
                                    d8u_10:	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_11		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_12		;else
                                    d8u_11:	sec			;    set carry to be shifted into result
                                    
                                    d8u_12:	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_13		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_14		;else
                                    d8u_13:	sec			;    set carry to be shifted into result
                                    
                                    d8u_14:	rol	dd8u		;shift left dividend
                                    	rol	drem8u		;shift dividend into remainder
                                    	sub	drem8u,dv8u	;remainder = remainder - divisor
                                    	brcc	d8u_15		;if result negative
                                    	add	drem8u,dv8u	;    restore remainder
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d8u_16		;else
                                    d8u_15:	sec			;    set carry to be shifted into result
                                    
                                    d8u_16:	rol	dd8u		;shift left dividend
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "div16u" - 16/16 Bit Unsigned Division
                                    ;*
                                    ;* This subroutine divides the two 16-bit numbers 
                                    ;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor). 
                                    ;* The result is placed in "dres16uH:dres16uL" and the remainder in
                                    ;* "drem16uH:drem16uL".
                                    ;*  
                                    ;* Number of words	:196 + return
                                    ;* Number of cycles	:148/173/196 (Min/Avg/Max)
                                    ;* Low registers used	:2 (drem16uL,drem16uH)
                                    ;* High registers used  :4 (dres16uL/dd16uL,dres16uH/dd16uH,dv16uL,dv16uH)
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	drem16uL=r14
                                    .def	drem16uH=r15
                                    .def	dres16uL=r16
                                    .def	dres16uH=r17
                                    .def	dd16uL	=r16
                                    .def	dd16uH	=r17
                                    .def	dv16uL	=r18
                                    .def	dv16uH	=r19
                                    
                                    ;***** Code
                                    
                                    div16u:	clr	drem16uL	;clear remainder Low byte
                                    	sub	drem16uH,drem16uH;clear remainder High byte and carry
                                    
                                    	rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_1		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_2		;else
                                    d16u_1:	sec			;    set carry to be shifted into result
                                    
                                    d16u_2:	rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_3		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_4		;else
                                    d16u_3:	sec			;    set carry to be shifted into result
                                    
                                    d16u_4:	rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_5		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_6		;else
                                    d16u_5:	sec			;    set carry to be shifted into result
                                    
                                    d16u_6:	rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_7		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_8		;else
                                    d16u_7:	sec			;    set carry to be shifted into result
                                    
                                    d16u_8:	rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_9		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_10		;else
                                    d16u_9:	sec			;    set carry to be shifted into result
                                    
                                    d16u_10:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_11		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_12		;else
                                    d16u_11:sec			;    set carry to be shifted into result
                                    
                                    d16u_12:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_13		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_14		;else
                                    d16u_13:sec			;    set carry to be shifted into result
                                    
                                    d16u_14:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_15		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_16		;else
                                    d16u_15:sec			;    set carry to be shifted into result
                                    
                                    d16u_16:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_17		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_18		;else
                                    d16u_17:	sec			;    set carry to be shifted into result
                                    
                                    d16u_18:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_19		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_20		;else
                                    d16u_19:sec			;    set carry to be shifted into result
                                    
                                    d16u_20:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_21		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_22		;else
                                    d16u_21:sec			;    set carry to be shifted into result
                                    
                                    d16u_22:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_23		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_24		;else
                                    d16u_23:sec			;    set carry to be shifted into result
                                    
                                    d16u_24:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_25		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_26		;else
                                    d16u_25:sec			;    set carry to be shifted into result
                                    
                                    d16u_26:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_27		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_28		;else
                                    d16u_27:sec			;    set carry to be shifted into result
                                    
                                    d16u_28:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_29		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_30		;else
                                    d16u_29:sec			;    set carry to be shifted into result
                                    
                                    d16u_30:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	rol	drem16uL	;shift dividend into remainder
                                    	rol	drem16uH
                                    	sub	drem16uL,dv16uL	;remainder = remainder - divisor
                                    	sbc	drem16uH,dv16uH	;
                                    	brcc	d16u_31		;if result negative
                                    	add	drem16uL,dv16uL	;    restore remainder
                                    	adc	drem16uH,dv16uH
                                    	clc			;    clear carry to be shifted into result
                                    	rjmp	d16u_32		;else
                                    d16u_31:sec			;    set carry to be shifted into result
                                    
                                    d16u_32:rol	dd16uL		;shift left dividend
                                    	rol	dd16uH
                                    	ret
                                    
                                    
                                    
                                    ;****************************************************************************
                                    ;*
                                    ;* Test Program
                                    ;*
                                    ;* This program calls all the subroutines as an example of usage and to 
                                    ;* verify correct verification.
                                    ;*
                                    ;****************************************************************************
                                    
                                    ;***** Main Program Register variables
                                    
                                    .def	temp	=r16		;temporary storage variable
                                    
                                    ;***** Code
                                    RESET:
                                    ;---------------------------------------------------------------
                                    ;Include these lines for devices with SRAM
                                    ;	ldi	temp,low(RAMEND)
                                    ;	out	SPL,temp	
                                    ;	ldi	temp,high(RAMEND)
                                    ;	out	SPH,temp	;init Stack Pointer
                                    ;---------------------------------------------------------------
                                    
                                    ;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4)
                                    
                                    	ldi	mc8u,250
                                    	ldi	mp8u,4
                                    	rcall	mpy8u		;result: m8uH:m8uL = $03e8 (1000)
                                    
                                    ;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000)
                                    	ldi	mc16uL,low(5050)
                                    	ldi	mc16uH,high(5050)
                                    	ldi	mp16uL,low(10000)
                                    	ldi	mp16uH,high(10000)
                                    	rcall	mpy16u		;result: m16u3:m16u2:m16u1:m16u0
                                    				;=$030291a0 (50,500,000)
                                    
                                    ;***** Divide Two Unsigned 8-Bit Numbers (100/3)
                                    	ldi	dd8u,100
                                    	ldi	dv8u,3
                                    	rcall	div8u		;result: 	$21 (33)
                                    				;remainder:	$01 (1)
                                    
                                    ;***** Divide Two Unsigned 16-Bit Numbers (50,000/24,995)
                                    	ldi	dd16uL,low(50000)
                                    	ldi	dd16uH,high(50000)
                                    	ldi	dv16uL,low(24995)
                                    	ldi	dv16uH,high(24995)
                                    	rcall	div16u		;result:	$0002 (2)
                                    				;remainder:	$000a (10)
                                    
                                    forever:rjmp	forever
                                    
                                    
                                    

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language