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AVR I2C MASTER PROTOCOL (AVR 300)

                                    ;**** A P P L I C A T I O N   N O T E   A V R 3 0 0 ************************
                                    ;*
                                    ;* Title		: I2C (Single) Master Implementation
                                    ;* Version		: 1.0 (BETA)
                                    ;* Last updated		: 97.08.27
                                    ;* Target		: AT90Sxxxx (any AVR device)
                                    ;*
                                    ;* Support email	: avr@atmel.com
                                    ;*
                                    ;* DESCRIPTION
                                    ;* 	Basic routines for communicating with I2C slave devices. This
                                    ;*	"single" master implementation is limited to one bus master on the
                                    ;*	I2C bus. Most applications do not need the multimaster ability
                                    ;*	the I2C bus provides. A single master implementation uses, by far,
                                    ;*	less resources and is less XTAL frequency dependent.
                                    ;*
                                    ;*	Some features :
                                    ;*	* All interrupts are free, and can be used for other activities.
                                    ;*	* Supports normal and fast mode.
                                    ;*	* Supports both 7-bit and 10-bit addressing.
                                    ;*	* Supports the entire AVR microcontroller family.
                                    ;*
                                    ;*	Main I2C functions :
                                    ;*	'i2c_start' -		Issues a start condition and sends address
                                    ;*				and transfer direction.
                                    ;*	'i2c_rep_start' -	Issues a repeated start condition and sends
                                    ;*				address and transfer direction.
                                    ;*	'i2c_do_transfer' -	Sends or receives data depending on
                                    ;*				direction given in address/dir byte.
                                    ;*	'i2c_stop' -		Terminates the data transfer by issue a
                                    ;*				stop condition.
                                    ;*
                                    ;* USAGE
                                    ;*	Transfer formats is described in the AVR300 documentation.
                                    ;*	(An example is shown in the 'main' code).	
                                    ;*
                                    ;* NOTES
                                    ;*	The I2C routines can be called either from non-interrupt or
                                    ;*	interrupt routines, not both.
                                    ;*
                                    ;* STATISTICS
                                    ;*	Code Size	: 81 words (maximum)
                                    ;*	Register Usage	: 4 High, 0 Low
                                    ;*	Interrupt Usage	: None
                                    ;*	Other Usage	: Uses two I/O pins on port D
                                    ;*	XTAL Range	: N/A
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;**** Includes ****
                                    
                                    .include "1200def.inc"			; change if an other device is used
                                    
                                    ;**** Global I2C Constants ****
                                    
                                    .equ	SCLP	= 1			; SCL Pin number (port D)
                                    .equ	SDAP	= 0			; SDA Pin number (port D)
                                    
                                    .equ	b_dir	= 0			; transfer direction bit in i2cadr
                                    
                                    .equ	i2crd	= 1
                                    .equ	i2cwr	= 0
                                    
                                    ;**** Global Register Variables ****
                                    
                                    .def	i2cdelay= r16			; Delay loop variable
                                    .def	i2cdata	= r17			; I2C data transfer register
                                    .def	i2cadr	= r18			; I2C address and direction register
                                    .def	i2cstat	= r19			; I2C bus status register
                                    
                                    ;**** Interrupt Vectors ****
                                    
                                    	rjmp	RESET			; Reset handle
                                    ;	( rjmp	EXT_INT0 )		; ( IRQ0 handle )
                                    ;	( rjmp	TIM0_OVF )		; ( Timer 0 overflow handle )
                                    ;	( rjmp	ANA_COMP )		; ( Analog comparator handle )
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_hp_delay
                                    ;*	i2c_qp_delay
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	hp - half i2c clock period delay (normal: 5.0us / fast: 1.3us)
                                    ;*	qp - quarter i2c clock period delay (normal: 2.5us / fast: 0.6us)
                                    ;*
                                    ;*	SEE DOCUMENTATION !!!
                                    ;*
                                    ;* USAGE
                                    ;*	no parameters
                                    ;*
                                    ;* RETURN
                                    ;*	none
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_hp_delay:
                                    	ldi	i2cdelay,2
                                    i2c_hp_delay_loop:
                                    	dec	i2cdelay
                                    	brne	i2c_hp_delay_loop
                                    	ret
                                    
                                    i2c_qp_delay:
                                    	ldi	i2cdelay,1	
                                    i2c_qp_delay_loop:
                                    	dec	i2cdelay
                                    	brne	i2c_qp_delay_loop
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_rep_start
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Assert repeated start condition and sends slave address.
                                    ;*
                                    ;* USAGE
                                    ;*	i2cadr - Contains the slave address and transfer direction.
                                    ;*
                                    ;* RETURN
                                    ;*	Carry flag - Cleared if a slave responds to the address.
                                    ;*
                                    ;* NOTE
                                    ;*	IMPORTANT! : This funtion must be directly followed by i2c_start.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_rep_start:
                                    	sbi	DDRD,SCLP		; force SCL low
                                    	cbi	DDRD,SDAP		; release SDA
                                    	rcall	i2c_hp_delay		; half period delay
                                    	cbi	DDRD,SCLP		; release SCL
                                    	rcall	i2c_qp_delay		; quarter period delay
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_start
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Generates start condition and sends slave address.
                                    ;*
                                    ;* USAGE
                                    ;*	i2cadr - Contains the slave address and transfer direction.
                                    ;*
                                    ;* RETURN
                                    ;*	Carry flag - Cleared if a slave responds to the address.
                                    ;*
                                    ;* NOTE
                                    ;*	IMPORTANT! : This funtion must be directly followed by i2c_write.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_start:				
                                    	mov	i2cdata,i2cadr		; copy address to transmitt register
                                    	sbi	DDRD,SDAP		; force SDA low
                                    	rcall	i2c_qp_delay		; quarter period delay
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_write
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Writes data (one byte) to the I2C bus. Also used for sending
                                    ;*	the address.
                                    ;*
                                    ;* USAGE
                                    ;*	i2cdata - Contains data to be transmitted.
                                    ;*
                                    ;* RETURN
                                    ;*	Carry flag - Set if the slave respond transfer.
                                    ;*
                                    ;* NOTE
                                    ;*	IMPORTANT! : This funtion must be directly followed by i2c_get_ack.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_write:
                                    	sec				; set carry flag
                                    	rol	i2cdata			; shift in carry and out bit one
                                    	rjmp	i2c_write_first
                                    i2c_write_bit:
                                    	lsl	i2cdata			; if transmit register empty
                                    i2c_write_first:
                                    	breq	i2c_get_ack		;	goto get acknowledge
                                    	sbi	DDRD,SCLP		; force SCL low
                                    
                                    	brcc	i2c_write_low		; if bit high
                                    	nop				;	(equalize number of cycles)
                                    	cbi	DDRD,SDAP		;	release SDA
                                    	rjmp	i2c_write_high
                                    i2c_write_low:				; else
                                    	sbi	DDRD,SDAP		;	force SDA low
                                    	rjmp	i2c_write_high		;	(equalize number of cycles)
                                    i2c_write_high:
                                    	rcall	i2c_hp_delay		; half period delay
                                    	cbi	DDRD,SCLP		; release SCL
                                    	rcall	i2c_hp_delay		; half period delay
                                    
                                    	rjmp	i2c_write_bit
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_get_ack
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Get slave acknowledge response.
                                    ;*
                                    ;* USAGE
                                    ;*	(used only by i2c_write in this version)
                                    ;*
                                    ;* RETURN
                                    ;*	Carry flag - Cleared if a slave responds to a request.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_get_ack:
                                    	sbi	DDRD,SCLP		; force SCL low
                                    	cbi	DDRD,SDAP		; release SDA
                                    	rcall	i2c_hp_delay		; half period delay
                                    	cbi	DDRD,SCLP		; release SCL
                                    
                                    i2c_get_ack_wait:
                                    	sbis	PIND,SCLP		; wait SCL high 
                                    					;(In case wait states are inserted)
                                    	rjmp	i2c_get_ack_wait
                                    
                                    	clc				; clear carry flag
                                    	sbic	PIND,SDAP		; if SDA is high
                                    	sec				;	set carry flag
                                    	rcall	i2c_hp_delay		; half period delay
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_do_transfer
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Executes a transfer on bus. This is only a combination of i2c_read
                                    ;*	and i2c_write for convenience.
                                    ;*
                                    ;* USAGE
                                    ;*	i2cadr - Must have the same direction as when i2c_start was called.
                                    ;*	see i2c_read and i2c_write for more information.
                                    ;*
                                    ;* RETURN
                                    ;*	(depends on type of transfer, read or write)
                                    ;*
                                    ;* NOTE
                                    ;*	IMPORTANT! : This funtion must be directly followed by i2c_read.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_do_transfer:
                                    	sbrs	i2cadr,b_dir		; if dir = write
                                    	rjmp	i2c_write		;	goto write data
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_read
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Reads data (one byte) from the I2C bus.
                                    ;*
                                    ;* USAGE
                                    ;*	Carry flag - 	If set no acknowledge is given to the slave
                                    ;*			indicating last read operation before a STOP.
                                    ;*			If cleared acknowledge is given to the slave
                                    ;*			indicating more data.
                                    ;*
                                    ;* RETURN
                                    ;*	i2cdata - Contains received data.
                                    ;*
                                    ;* NOTE
                                    ;*	IMPORTANT! : This funtion must be directly followed by i2c_put_ack.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_read:
                                    	rol	i2cstat			; store acknowledge
                                    					; (used by i2c_put_ack)
                                    	ldi	i2cdata,0x01		; data = 0x01
                                    i2c_read_bit:				; do
                                    	sbi	DDRD,SCLP		; 	force SCL low
                                    	rcall	i2c_hp_delay		;	half period delay
                                    
                                    	cbi	DDRD,SCLP		;	release SCL
                                    	rcall	i2c_hp_delay		;	half period delay
                                    
                                    	clc				;	clear carry flag
                                    	sbic	PIND,SDAP		;	if SDA is high
                                    	sec				;		set carry flag
                                    
                                    	rol	i2cdata			; 	store data bit
                                    	brcc	i2c_read_bit		; while receive register not full
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_put_ack
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Put acknowledge.
                                    ;*
                                    ;* USAGE
                                    ;*	(used only by i2c_read in this version)
                                    ;*
                                    ;* RETURN
                                    ;*	none
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_put_ack:
                                    	sbi	DDRD,SCLP		; force SCL low
                                    
                                    	ror	i2cstat			; get status bit
                                    	brcc	i2c_put_ack_low		; if bit low goto assert low
                                    	cbi	DDRD,SDAP		;	release SDA
                                    	rjmp	i2c_put_ack_high
                                    i2c_put_ack_low:			; else
                                    	sbi	DDRD,SDAP		;	force SDA low
                                    i2c_put_ack_high:
                                    
                                    	rcall	i2c_hp_delay		; half period delay
                                    	cbi	DDRD,SCLP		; release SCL
                                    i2c_put_ack_wait:
                                    	sbis	PIND,SCLP		; wait SCL high
                                    	rjmp	i2c_put_ack_wait
                                    	rcall	i2c_hp_delay		; half period delay
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_stop
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Assert stop condition.
                                    ;*
                                    ;* USAGE
                                    ;*	No parameters.
                                    ;*
                                    ;* RETURN
                                    ;*	None.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_stop:
                                    	sbi	DDRD,SCLP		; force SCL low
                                    	sbi	DDRD,SDAP		; force SDA low
                                    	rcall	i2c_hp_delay		; half period delay
                                    	cbi	DDRD,SCLP		; release SCL
                                    	rcall	i2c_qp_delay		; quarter period delay
                                    	cbi	DDRD,SDAP		; release SDA
                                    	rcall	i2c_hp_delay		; half period delay
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* FUNCTION
                                    ;*	i2c_init
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Initialization of the I2C bus interface.
                                    ;*
                                    ;* USAGE
                                    ;*	Call this function once to initialize the I2C bus. No parameters
                                    ;*	are required.
                                    ;*
                                    ;* RETURN
                                    ;*	None
                                    ;*
                                    ;* NOTE
                                    ;*	PORTD and DDRD pins not used by the I2C bus interface will be
                                    ;*	set to Hi-Z (!).
                                    ;*
                                    ;* COMMENT
                                    ;*	This function can be combined with other PORTD initializations.
                                    ;*
                                    ;***************************************************************************
                                    
                                    i2c_init:
                                    	clr	i2cstat			; clear I2C status register (used
                                    					; as a temporary register)
                                    	out	PORTD,i2cstat		; set I2C pins to open colector
                                    	out	DDRD,i2cstat
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* PROGRAM
                                    ;*	main - Test of I2C master implementation
                                    ;*
                                    ;* DESCRIPTION
                                    ;*	Initializes I2C interface and shows an example of using it.
                                    ;*
                                    ;***************************************************************************
                                    
                                    RESET:
                                    main:	rcall	i2c_init		; initialize I2C interface
                                    
                                    ;**** Write data => Adr(00) = 0x55 ****
                                    
                                    	ldi	i2cadr,$A0+i2cwr	; Set device address and write
                                    	rcall	i2c_start		; Send start condition and address
                                    
                                    	ldi	i2cdata,$00		; Write word address (0x00)
                                    	rcall	i2c_do_transfer		; Execute transfer
                                    
                                    	ldi	i2cdata,$55		; Set write data to 01010101b
                                    	rcall	i2c_do_transfer		; Execute transfer
                                    
                                    	rcall	i2c_stop		; Send stop condition
                                    
                                    ;**** Read data => i2cdata = Adr(00) ****
                                    
                                    	ldi	i2cadr,$A0+i2cwr	; Set device address and write
                                    	rcall	i2c_start		; Send start condition and address
                                    
                                    	ldi	i2cdata,$00		; Write word address
                                    	rcall	i2c_do_transfer		; Execute transfer
                                    
                                    	ldi	i2cadr,$A0+i2crd	; Set device address and read
                                    	rcall	i2c_rep_start		; Send repeated start condition and address
                                    
                                    	sec				; Set no acknowledge (read is followed by a stop condition)
                                    	rcall	i2c_do_transfer		; Execute transfer (read)
                                    
                                    	rcall	i2c_stop		; Send stop condition - releases bus
                                    
                                    	rjmp	main			; Loop forewer
                                    
                                    ;**** End of File ****
                                    
                                    
                                    
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language