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BCD MATH (AVR 204)

                                    ;**** A P P L I C A T I O N   N O T E   A V R 2 0 4 ************************
                                    ;*
                                    ;* Title:		BCD Arithmetics
                                    ;* Version:		1.1
                                    ;* Last updated:	97.07.04
                                    ;* Target:		AT90Sxxxx (All AVR Devices)
                                    ;*
                                    ;* Support E-mail:	avr@atmel.com
                                    ;* 
                                    ;* DESCRIPTION
                                    ;* This Application Note lists subroutines for the following Binary Coded
                                    ;* Decimal arithmetic applications:
                                    ;*
                                    ;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x)
                                    ;* Binary 8 to BCD Conversion
                                    ;* BCD to Binary 16 Conversion
                                    ;* BCD to Binary 8 Conversion
                                    ;* 2-Digit BCD Addition
                                    ;* 2-Digit BCD Subtraction
                                    ;*
                                    ;***************************************************************************
                                    
                                    .include "8515def.inc"
                                    
                                    	rjmp	RESET	;reset handle
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "bin2BCD16" - 16-bit Binary to BCD conversion
                                    ;*
                                    ;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit 
                                    ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0).
                                    ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2.
                                    ;*  
                                    ;* Number of words	:25
                                    ;* Number of cycles	:751/768 (Min/Max)
                                    ;* Low registers used	:3 (tBCD0,tBCD1,tBCD2) 
                                    ;* High registers used  :4(fbinL,fbinH,cnt16a,tmp16a)	
                                    ;* Pointers used	:Z
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .equ	AtBCD0	=13		;address of tBCD0
                                    .equ	AtBCD2	=15		;address of tBCD1
                                    
                                    .def	tBCD0	=r13		;BCD value digits 1 and 0
                                    .def	tBCD1	=r14		;BCD value digits 3 and 2
                                    .def	tBCD2	=r15		;BCD value digit 4
                                    .def	fbinL	=r16		;binary value Low byte
                                    .def	fbinH	=r17		;binary value High byte
                                    .def	cnt16a	=r18		;loop counter
                                    .def	tmp16a	=r19		;temporary value
                                    
                                    ;***** Code
                                    
                                    bin2BCD16:
                                    	ldi	cnt16a,16	;Init loop counter	
                                    	clr	tBCD2		;clear result (3 bytes)
                                    	clr	tBCD1		
                                    	clr	tBCD0		
                                    	clr	ZH		;clear ZH (not needed for AT90Sxx0x)
                                    bBCDx_1:lsl	fbinL		;shift input value
                                    	rol	fbinH		;through all bytes
                                    	rol	tBCD0		;
                                    	rol	tBCD1
                                    	rol	tBCD2
                                    	dec	cnt16a		;decrement loop counter
                                    	brne	bBCDx_2		;if counter not zero
                                    	ret			;   return
                                    
                                    bBCDx_2:ldi	r30,AtBCD2+1	;Z points to result MSB + 1
                                    bBCDx_3:
                                    	ld	tmp16a,-Z	;get (Z) with pre-decrement
                                    ;----------------------------------------------------------------
                                    ;For AT90Sxx0x, substitute the above line with:
                                    ;
                                    ;	dec	ZL
                                    ;	ld	tmp16a,Z
                                    ;
                                    ;----------------------------------------------------------------
                                    	subi	tmp16a,-$03	;add 0x03
                                    	sbrc	tmp16a,3	;if bit 3 not clear
                                    	st	Z,tmp16a	;	store back
                                    	ld	tmp16a,Z	;get (Z)
                                    	subi	tmp16a,-$30	;add 0x30
                                    	sbrc	tmp16a,7	;if bit 7 not clear
                                    	st	Z,tmp16a	;	store back
                                    	cpi	ZL,AtBCD0	;done all three?
                                    	brne	bBCDx_3		;loop again if not
                                    	rjmp	bBCDx_1		
                                    
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "bin2BCD8" - 8-bit Binary to BCD conversion
                                    ;*
                                    ;* This subroutine converts an 8-bit number (fbin) to a 2-digit 
                                    ;* BCD number (tBCDH:tBCDL).
                                    ;*  
                                    ;* Number of words	:6 + return
                                    ;* Number of cycles	:5/50 (Min/Max) + return
                                    ;* Low registers used	:None
                                    ;* High registers used  :2 (fbin/tBCDL,tBCDH)
                                    ;*
                                    ;* Included in the code are lines to add/replace for packed BCD output.	
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	fbin	=r16		;8-bit binary value
                                    .def	tBCDL	=r16		;BCD result MSD
                                    .def	tBCDH	=r17		;BCD result LSD
                                    
                                    ;***** Code
                                    
                                    bin2bcd8:
                                    	clr	tBCDH		;clear result MSD
                                    bBCD8_1:subi	fbin,10		;input = input - 10
                                    	brcs	bBCD8_2		;abort if carry set
                                    	inc	tBCDH		;inc MSD
                                    ;---------------------------------------------------------------------------
                                    ;				;Replace the above line with this one
                                    ;				;for packed BCD output				
                                    ;	subi	tBCDH,-$10 	;tBCDH = tBCDH + 10
                                    ;---------------------------------------------------------------------------
                                    	rjmp	bBCD8_1		;loop again
                                    bBCD8_2:subi	fbin,-10	;compensate extra subtraction
                                    ;---------------------------------------------------------------------------
                                    ;				;Add this line for packed BCD output
                                    ;	add	fbin,tBCDH	
                                    ;---------------------------------------------------------------------------	
                                    	ret
                                    
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "BCD2bin16" - BCD to 16-Bit Binary Conversion
                                    ;*
                                    ;* This subroutine converts a 5-digit packed BCD number represented by 
                                    ;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL).
                                    ;* MSD of the 5-digit number must be placed in the lowermost nibble of fBCD2.
                                    ;* 
                                    ;* Let "abcde" denote the 5-digit number. The conversion is done by
                                    ;* computing the formula: 10(10(10(10a+b)+c)+d)+e.
                                    ;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation 
                                    ;* which is repeated four times during the computation.
                                    ;*  
                                    ;* Number of words	:30 
                                    ;* Number of cycles	:108 
                                    ;* Low registers used	:4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH)
                                    ;* High registers used  :4 (fBCD0,fBCD1,fBCD2,adder)	
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** "mul10a"/"mul10b" Subroutine Register Variables
                                    
                                    .def	copyL	=r12		;temporary register
                                    .def	copyH	=r13		;temporary register
                                    .def	mp10L	=r14		;Low byte of number to be multiplied by 10
                                    .def	mp10H	=r15		;High byte of number to be multiplied by 10
                                    .def	adder	=r19		;value to add after multiplication	
                                    
                                    ;***** Code
                                    
                                    mul10a:	;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high nibble 
                                    	swap	adder
                                    mul10b:	;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low nibble 
                                    	mov	copyL,mp10L	;make copy
                                    	mov	copyH,mp10H
                                    	lsl	mp10L		;multiply original by 2
                                    	rol	mp10H
                                    	lsl	copyL		;multiply copy by 2
                                    	rol	copyH		
                                    	lsl	copyL		;multiply copy by 2 (4)
                                    	rol	copyH		
                                    	lsl	copyL		;multiply copy by 2 (8)
                                    	rol	copyH		
                                    	add	mp10L,copyL	;add copy to original
                                    	adc	mp10H,copyH	
                                    	andi	adder,0x0f	;mask away upper nibble of adder
                                    	add	mp10L,adder	;add lower nibble of adder
                                    	brcc	m10_1		;if carry not cleared
                                    	inc	mp10H		;	inc high byte
                                    m10_1:	ret	
                                    
                                    ;***** Main Routine Register Variables
                                    
                                    .def	tbinL	=r14		;Low byte of binary result (same as mp10L)
                                    .def	tbinH	=r15		;High byte of binary result (same as mp10H)
                                    .def	fBCD0	=r16		;BCD value digits 1 and 0
                                    .def	fBCD1	=r17		;BCD value digits 2 and 3
                                    .def	fBCD2	=r18		;BCD value digit 5
                                    
                                    ;***** Code
                                    
                                    BCD2bin16:
                                    	andi	fBCD2,0x0f	;mask away upper nibble of fBCD2
                                    	clr	mp10H		
                                    	mov	mp10L,fBCD2	;mp10H:mp10L = a
                                    	mov	adder,fBCD1
                                    	rcall	mul10a		;mp10H:mp10L = 10a+b
                                    	mov	adder,fBCD1
                                    	rcall	mul10b		;mp10H:mp10L = 10(10a+b)+c
                                    	mov	adder,fBCD0		
                                    	rcall	mul10a		;mp10H:mp10L = 10(10(10a+b)+c)+d
                                    	mov	adder,fBCD0
                                    	rcall	mul10b		;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
                                    	ret
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "BCD2bin8" - BCD to 8-bit binary conversion
                                    ;*
                                    ;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an 
                                    ;* 8-bit number (tbin).
                                    ;*  
                                    ;* Number of words	:4 + return
                                    ;* Number of cycles	:3/48 (Min/Max) + return
                                    ;* Low registers used	:None
                                    ;* High registers used  :2 (tbin/fBCDL,fBCDH)	
                                    ;*
                                    ;* Modifications to make the routine accept a packed BCD number is indicated
                                    ;* as comments in the code. If the modifications are used, fBCDH shall be
                                    ;* loaded with the BCD number to convert prior to calling the routine.
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	tbin	=r16		;binary result
                                    .def	fBCDL	=r16		;lower digit of BCD input
                                    .def	fBCDH	=r17		;higher digit of BCD input
                                    
                                    ;***** Code
                                    
                                    BCD2bin8:
                                    ;--------------------------------------------------------------------------
                                    ;|				;For packed BCD input, add these two lines
                                    ;|	mov	tbin,fBCDH	;copy input to result
                                    ;|	andi	tbin,$0f	;clear higher nibble of result
                                    ;--------------------------------------------------------------------------
                                    
                                    BCDb8_0:subi	fBCDH,1		;fBCDH = fBCDH - 1
                                    	brcs	BCDb8_1		;if carry not set
                                    ;--------------------------------------------------------------------------
                                    ;|				;For packed BCD input, replace the above
                                    ;|				;two lines with these.
                                    ;|	subi	fBCDH,$10	;MSD = MSD - 1
                                    ;|	brmi	BCDb8_1		;if Zero flag not set
                                    ;--------------------------------------------------------------------------
                                    	subi	tbin,-10	;    result = result + 10
                                    	rjmp	BCDb8_0		;    loop again
                                    BCDb8_1:ret			;else return
                                    
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "BCDadd" - 2-digit packed BCD addition
                                    ;*
                                    ;* This subroutine adds the two unsigned 2-digit BCD numbers 
                                    ;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow 
                                    ;* carry in "BCD2".
                                    ;*  
                                    ;* Number of words	:19
                                    ;* Number of cycles	:17/20 (Min/Max)
                                    ;* Low registers used	:None
                                    ;* High registers used  :3 (BCD1,BCD2,tmpadd)	
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	BCD1	=r16		;BCD input value #1
                                    .def	BCD2	=r17		;BCD input value #2
                                    .def	tmpadd	=r18		;temporary register
                                    
                                    ;***** Code
                                    
                                    BCDadd:
                                    	ldi	tmpadd,6	;value to be added later
                                    	add	BCD1,BCD2	;add the numbers binary
                                    	clr	BCD2		;clear BCD carry
                                    	brcc	add_0		;if carry not clear
                                    	ldi	BCD2,1		;    set BCD carry
                                    add_0:	brhs	add_1		;if half carry not set
                                    	add	BCD1,tmpadd	;    add 6 to LSD
                                    	brhs	add_2		;    if half carry not set (LSD <= 9)
                                    	subi	BCD1,6		;        restore value
                                    	rjmp	add_2		;else
                                    add_1:	add	BCD1,tmpadd	;    add 6 to LSD
                                    add_2:	swap	tmpadd
                                    	add	BCD1,tmpadd	;add 6 to MSD
                                    	brcs	add_4		;if carry not set (MSD <= 9)
                                    	sbrs	BCD2,0		;    if previous carry not set
                                    	subi	BCD1,$60	;	restore value 
                                    add_3:	ret			;else
                                    add_4:	ldi	BCD2,1		;    set BCD carry
                                    	ret
                                    
                                    
                                    
                                    ;***************************************************************************
                                    ;*
                                    ;* "BCDsub" - 2-digit packed BCD subtraction
                                    ;*
                                    ;* This subroutine subtracts the two unsigned 2-digit BCD numbers 
                                    ;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and 
                                    ;* the underflow carry in "BCDb".
                                    ;*  
                                    ;* Number of words	:13
                                    ;* Number of cycles	:12/17 (Min/Max)
                                    ;* Low registers used	:None
                                    ;* High registers used  :2 (BCDa,BCDb)	
                                    ;*
                                    ;***************************************************************************
                                    
                                    ;***** Subroutine Register Variables
                                    
                                    .def	BCDa	=r16		;BCD input value #1
                                    .def	BCDb	=r17		;BCD input value #2
                                    
                                    ;***** Code
                                    
                                    BCDsub:
                                    	sub	BCDa,BCDb	;subtract the numbers binary
                                    	clr	BCDb
                                    	brcc	sub_0		;if carry not clear
                                    	ldi	BCDb,1		;    store carry in BCDB1, bit 0
                                    sub_0:	brhc	sub_1		;if half carry not clear
                                    	subi	BCDa,$06	;    LSD = LSD - 6
                                    sub_1:	sbrs	BCDb,0		;if previous carry not set
                                    	ret			;    return
                                    	subi	BCDa,$60	;subtract 6 from MSD
                                    	ldi	BCDb,1		;set underflow carry
                                    	brcc	sub_2		;if carry not clear
                                    	ldi	BCDb,1		;    clear underflow carry	
                                    sub_2:	ret			
                                    
                                    
                                    
                                    ;****************************************************************************
                                    ;*
                                    ;* Test Program
                                    ;*
                                    ;* This program calls all the subroutines as an example of usage and to 
                                    ;* verify correct operation.
                                    ;*
                                    ;****************************************************************************
                                    
                                    ;***** Main Program Register variables
                                    
                                    .def	temp	=r16		;temporary storage variable
                                    
                                    ;***** Code
                                    
                                    RESET:
                                    	ldi	temp,low(RAMEND)
                                    	out	SPL,temp
                                    	ldi	temp,high(RAMEND)
                                    	out	SPH,temp	;init Stack Pointer (remove for AT90Sxx0x)
                                    
                                    ;***** Convert 54,321 to 2.5-byte packed BCD format
                                    
                                    	ldi	fbinL,low(54321)
                                    	ldi	fbinH,high(54321)
                                    	rcall	bin2BCD16	;result: tBCD2:tBCD1:tBCD0 = $054321
                                    
                                    ;***** Convert 55 to 2-byte BCD 
                                    
                                    	ldi	fbin,55
                                    	rcall	bin2BCD8	;result: tBCDH:tBCDL = 0505
                                    
                                    ;***** Convert $065535 to a 16-bit binary number
                                    	ldi	fBCD2,$06
                                    	ldi	fBCD1,$55
                                    	ldi	fBCD0,$35
                                    	rcall	BCD2bin16	;result: tbinH:tbinL = $ffff (65,535)
                                    
                                    ;***** Convert $0403 (43) to an 8-bit binary number
                                    	ldi	fBCDL,3
                                    	ldi	fBCDH,4
                                    	rcall	BCD2bin8	;result: tbin = $2b (43)
                                    
                                    ;***** Add BCD numbers 51 and 79
                                    	ldi	BCD1,$51
                                    	ldi	BCD2,$79
                                    	rcall	BCDadd		;result: BCD2:BCD1=$0130
                                    
                                    ;***** Subtract BCD numbers 72 - 28
                                    	ldi	BCDa,$72
                                    	ldi	BCDb,$28
                                    	rcall	BCDsub		;result: BCDb=$00 (positive result), BCDa=44
                                    
                                    ;***** Subtract BCD numbers 0 - 90
                                    	ldi	BCDa,$00
                                    	ldi	BCDb,$90
                                    	rcall	BCDsub		;result: BCDb=$01 (negative result), BCDa=10	
                                    
                                    
                                    
                                    forever:rjmp	forever
                                    
                                    
                                    
                                    
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language