Make your own free website on Tripod.com

The AVR Assembler Site

HOME
AVR ASM TUTOR
ASM FORUM
AVR BEGINNERS NET
TUTORIAL #2
MUL & DIV
FAST MUL & DIV
16 BIT MUL
16 BIT ADD & SUB
32 BIT MATH
16 BIT MATH
16 BIT DIV
24 BIT DIV
32 BIT DIV
FLOAT MATH
SQRT16
BCD CONVERSIONS
16 BIT BCD
DEC TO ASCII
INTEGER TO ASCII
HEX TO ASCII
MOVING AVG
FAST FOURIER
BLOCK COPY
LOAD PROG MEM
EPROM STORAGE
SERIAL EPROM
AT45 DATAFLASH
FLASH CARD
VFX SMIL
VFX MEM
BUBBLE SORT
CRC CHECK
XMODEM REC
UART 304
UART 305
UART 128
UART BUFF
USB TO RS232
AVR ISP
ISP 2313
ISP 1200
AVR SPI
I2C 300
I2C 302
I2C TWI26
I2C/TWI 128
I2C/TWI AT8
DALLAS-1W
DALLAS CRC
ETHERNET DRIVER
TEA PROTOCOL
ADC
10 BIT ADC
CHEAP ADC
PRECISION 8 BIT ADC
THERMOMETER
INFARED DECODER
LCD DRIVER FOR HD44xxx
LCD DRIVER FOR HD44780
LCD DRIVER FOR HD44780 #2
4x4 KEYPAD
KEYPAD LED MUX
AT/PS2 KEYBOARD
AT KEYBOARD
PS2 KEYBOARD
MEGA 8 BOOTLOADER
BOOTLOADER
ALARM CLOCK
REAL TIME CLOCK
90 DAY TIMER
DELAY ROUTINE
CALLER ID
DTMF GENERATOR
6 CHAN PWM
PWM 10K
ENCODER
STH-11
ATMEL CORP
AVR BUTTERFLY
AVR BOOK

DTMF GENERATOR (AVR 314)

                                    ;*************************************************************************** 
                                    ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 
                                    ;* 
                                    ;* Number : AVR314 
                                    ;* File Name : "dtmf.asm" 
                                    ;* Title : DTMF Generator 
                                    ;* Date : 00.06.27 
                                    ;* Version : 1.1 
                                    ;* Target MCU : Any AVR with SRAM, 8 I/O pins and PWM 
                                    ;* 
                                    ;* DESCRIPTION 
                                    ;* This Application note describes how to generate DTMF tones using a single 
                                    ;* 8 bit PWM output. 
                                    ;* 
                                    ;*************************************************************************** 
                                    
                                    .include "4414def.inc" 
                                    
                                    ;************************************************************************** 
                                    ; REGISTERS 
                                    ;************************************************************************** 
                                    .def XL_Tmp = r1 ; low part temporary register 
                                    .def XH_Tmp = r2 ; high part temporary register 
                                    
                                    ; Number of Element (Position) in LUT in Extended format 
                                    .def XL_LUTbExt = r3 ; number of LUT-Element of frequency a (low byte) 
                                    .def XH_LUTbExt = r4 ; number of LUT-Element of frequency a (high byte) 
                                    .def XL_LUTaExt = r5 ; number of LUT-Element of frequency b (low byte) 
                                    .def XH_LUTaExt = r6 ; number of LUT-Element of frequency b (high byte) 
                                    
                                    .def OCR_RelValb = r7 ; low frequency reload value to be written to OCR 
                                    .def OCR_RelVala = r8 ; High frequency reload value to be written to OCR 
                                    
                                    .def x_SWa = r9 ; step width in LUT to get high frequency 
                                    .def x_SWb = r10 ; step width in LUT to get low frequency 
                                    
                                    .def count = r18 ; temporary counter register 
                                    .def tmp = r16 ; temp register 
                                    
                                    .def input = r17 ; input from portB 
                                    
                                    ;************************************************************************** 
                                    ;************************************************************************** 
                                    .equ Xtal = 8000000 ; system clock frequency 
                                    .equ prescaler = 1 ; timer1 prescaler 
                                    .equ N_samples = 128 ; Number of samples in lookup table 
                                    .equ Fck = Xtal/prescaler ; timer1 working frequency 
                                    .equ delaycyc = 10 ; port B setup delay cycles 
                                    
                                    ;************************************************************************** 
                                    ; PROGRAM START - EXECUTION STARTS HERE 
                                    ;************************************************************************** 
                                    .cseg 
                                    .org $0 
                                    rjmp start ; Reset handler 
                                    .org OVF1addr 
                                    rjmp tim1_ovf ; Timer1 overflow Handle 
                                    
                                    ;************************************************************************** 
                                    ; Interrupt timer1 
                                    ;************************************************************************** 
                                    tim1_ovf: 
                                    push tmp ; Store temporary register 
                                    in tmp,SREG 
                                    push tmp ; Store status register 
                                    push ZL 
                                    push ZH ; Store Z-Pointer 
                                    push r0 ; Store R0 Register 
                                    
                                    ;high frequency 
                                    mov XL_Tmp,XL_LUTaExt 
                                    mov XH_Tmp,XH_LUTaExt 
                                    add XL_LUTaExt,x_SWa 
                                    clr tmp ; (tmp is cleared, but not the carry flag) 
                                    adc XH_LUTaExt,tmp ; Refresh pointer for the next sample 
                                    rcall getsample ; read from Sin Wave Sample Table 
                                    mov OCR_RelVala,r0 ; OCR_RelVala = high frequency value 
                                    
                                    ;low frequency 
                                    mov XL_Tmp,XL_LUTbExt 
                                    mov XH_Tmp,XH_LUTbExt 
                                    add XL_LUTbExt,x_SWb 
                                    clr tmp ; (tmp is cleared, but not the carry flag) 
                                    adc XH_LUTbExt,tmp ; refresh pointer for the next sample 
                                    rcall getsample ; read from Sin Wave Sample Table 
                                    mov OCR_RelValb,r0 ; OCR_RelValb = low frequency value 
                                    
                                    ; scale amplitude 
                                    ldi tmp,2 
                                    add OCR_RelValb,tmp 
                                    lsr OCR_RelValb 
                                    lsr OCR_RelValb ; divide 4 and round off 
                                    sub r0,OCR_RelValb ; 4/4 - 1/4 = 3/4 
                                    mov OCR_RelValb,r0 ; now OCR_RelValb has the right amplitude 
                                    
                                    clr tmp 
                                    out OCR1AH,tmp 
                                    mov tmp,OCR_RelVala 
                                    add tmp,OCR_RelValb 
                                    out OCR1AL,tmp ; send the sum of the two amplitudes to PWM 
                                    
                                    pop r0 ; Restore R0 Register 
                                    pop ZH 
                                    pop ZL ; Restore Z-Pointer 
                                    pop tmp 
                                    out SREG,tmp ; Restore SREG 
                                    pop tmp ; Restore temporary register; 
                                    reti 
                                    
                                    ;********************************* 
                                    ; RESET Interrupt 
                                    ;********************************* 
                                    start: 
                                    sbi DDRD,PD5 ; Set pin PD5 as output 
                                    ldi tmp,low(RAMEND) 
                                    out SPL,tmp 
                                    ldi tmp,high(RAMEND) 
                                    out SPH,tmp ; Initialize Stackpointer 
                                    
                                    ;Initialization of the registers 
                                    clr XL_LUTaExt 
                                    clr XH_LUTaExt 
                                    clr XL_LUTbExt 
                                    clr XH_LUTbExt ; Set both table ponters to 0x0000 
                                    
                                    ;enable timer1 interrupt 
                                    ldi tmp,(1< out TIMSK,tmp ; Enable Timer1_ovf interrupt 
                                    
                                    ;set timer1 PWM mode 
                                    ldi tmp,(1< out TCCR1A,tmp ; 8 bit PWM not reverse (Fck/510) 
                                    ldi tmp,(1< out TCCR1B,tmp ; prescaler = 1 
                                    sei ; Enable interrupts 
                                    
                                    ;************************************************************************** 
                                    ; MAIN 
                                    ; Read from portB (eg: using evaluation board switch) which 
                                    ; tone to generate, extract mixing high frequency 
                                    ; (column) and low frequency (row), and then 
                                    ; fix x_SWa and x_SWb 
                                    ; row -> PINB high nibble 
                                    ; column -> PINB low nibble 
                                    ;************************************************************************** 
                                    
                                    main: 
                                    ;high frequency (Esteem only high nibble that is row) 
                                    ;PB_High_Nibble: 
                                    ldi tmp,0x0F 
                                    out DDRB,tmp ; High nibble Input / Low nibble. Outp. 
                                    ldi tmp,0xF0 
                                    out PORTB,tmp ; High nibble PullUp / Low nibble Zero Outp. 
                                    rcall delay 
                                    clr count 
                                    in input,PINB 
                                    
                                    main10: 
                                    inc count 
                                    lsl input 
                                    brcc main20 
                                    ldi tmp,4 
                                    cp count,tmp 
                                    brne main10 
                                    clr x_SWb 
                                    clr count 
                                    rjmp main30 
                                    
                                    main20: 
                                    dec count 
                                    ldi ZL,low(frequencyL*2) 
                                    ldi ZH,high(frequencyL*2) 
                                    add ZL,count 
                                    clr tmp 
                                    adc ZH,tmp 
                                    lpm 
                                    mov x_SWb,r0 ; this is low frequency x_SW 
                                    clr count 
                                    
                                    ;low frequency 
                                    ;PB_Low_Nibble: 
                                    main30: 
                                    ldi tmp,0xF0 
                                    out DDRB,tmp ; High nibble. Outp. / Low nibble Input 
                                    ldi tmp,0x0F 
                                    out PORTB,tmp ; High nibble Zero Outp. / Low nibble PullUp 
                                    rcall delay 
                                    in input,PINB 
                                    swap input 
                                    
                                    main40: 
                                    inc count 
                                    lsl input 
                                    brcc main50 
                                    ldi tmp,4 
                                    cp count,tmp 
                                    brne main40 
                                    clr x_SWa 
                                    rjmp main 
                                    
                                    main50: ; there is a zero bit in count-1 position 
                                    dec count 
                                    ldi ZL,low(frequencyH*2) 
                                    ldi ZH,high(frequencyH*2) 
                                    add ZL,count 
                                    clr tmp 
                                    adc ZH,tmp 
                                    lpm 
                                    mov x_SWa,r0 ; this is high frequency x_SW 
                                    rjmp main 
                                    
                                    
                                    ;****************** DELAY *********************************** 
                                    ;**************************************************************** 
                                    delay: 
                                    ldi tmp,delaycyc 
                                    loop: 
                                    dec tmp 
                                    brne loop 
                                    ret 
                                    
                                    
                                    ;****************** GET SAMPLE ****************************** 
                                    ;**************************************************************** 
                                    getsample: 
                                    ldi tmp,0x0f 
                                    and XH_Tmp,tmp 
                                    
                                    ; ROUND - add four 
                                    ldi tmp,4 
                                    add XL_Tmp,tmp 
                                    clr tmp 
                                    adc XH_Tmp,tmp 
                                    
                                    ; shift (divide by eight): 
                                    lsr XH_Tmp 
                                    ror XL_Tmp 
                                    lsr XH_Tmp 
                                    ror XL_Tmp 
                                    lsr XH_Tmp 
                                    ror XL_Tmp 
                                    
                                    ldi tmp,0x7f 
                                    and XL_Tmp,tmp ; module 128 (samples number sine table) 
                                    
                                    ldi ZL,low(sine_tbl*2) 
                                    ldi ZH,high(sine_tbl*2) 
                                    add ZL,XL_Tmp 
                                    clr tmp 
                                    adc ZH,tmp ; Z is a pointer to the correct 
                                    ; sine_tbl value 
                                    lpm 
                                    ret 
                                    
                                    ;*************************** SIN TABLE ************************************* 
                                    ; Samples table : one period sampled on 128 samples and 
                                    ; quantized on 7 bit 
                                    ;****************************************************************************** 
                                    sine_tbl: 
                                    .db 64,67 
                                    .db 70,73 
                                    .db 76,79 
                                    .db 82,85 
                                    .db 88,91 
                                    .db 94,96 
                                    .db 99,102 
                                    .db 104,106 
                                    .db 109,111 
                                    .db 113,115 
                                    .db 117,118 
                                    .db 120,121 
                                    .db 123,124 
                                    .db 125,126 
                                    .db 126,127 
                                    .db 127,127 
                                    .db 127,127 
                                    .db 127,127 
                                    .db 126,126 
                                    .db 125,124 
                                    .db 123,121 
                                    .db 120,118 
                                    .db 117,115 
                                    .db 113,111 
                                    .db 109,106 
                                    .db 104,102 
                                    .db 99,96 
                                    .db 94,91 
                                    .db 88,85 
                                    .db 82,79 
                                    .db 76,73 
                                    .db 70,67 
                                    .db 64,60 
                                    .db 57,54 
                                    .db 51,48 
                                    .db 45,42 
                                    .db 39,36 
                                    .db 33,31 
                                    .db 28,25 
                                    .db 23,21 
                                    .db 18,16 
                                    .db 14,12 
                                    .db 10,9 
                                    .db 7,6 
                                    .db 4,3 
                                    .db 2,1 
                                    .db 1,0 
                                    .db 0,0 
                                    .db 0,0 
                                    .db 0,0 
                                    .db 1,1 
                                    .db 2,3 
                                    .db 4,6 
                                    .db 7,9 
                                    .db 10,12 
                                    .db 14,16 
                                    .db 18,21 
                                    .db 23,25 
                                    .db 28,31 
                                    .db 33,36 
                                    .db 39,42 
                                    .db 45,48 
                                    .db 51,54 
                                    .db 57,60 
                                    
                                    ;******************************* x_SW *********************************** 
                                    ;Table of x_SW (excess : x_SW = ROUND(8*N_samples*f*510/Fck) 
                                    ;************************************************************************** 
                                    
                                    ;high frequency (coloun) 
                                    ;1209hz ---> x_SW = 79 
                                    ;1336hz ---> x_SW = 87 
                                    ;1477hz ---> x_SW = 96 
                                    ;1633hz ---> x_SW = 107 
                                    
                                    frequencyH: 
                                    .db 107,96 
                                    .db 87,79 
                                    
                                    ;low frequency (row) 
                                    ;697hz ---> x_SW = 46 
                                    ;770hz ---> x_SW = 50 
                                    ;852hz ---> x_SW = 56 
                                    ;941hz ---> x_SW = 61 
                                    
                                    frequencyL: 
                                    .db 61,56 
                                    .db 50,46
                                    
                                 

Programming the AVR Microcontrollers in Assember Machine Language

This site is a member of WebRing.
To browse visit Here.

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language