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UART ROUTINES FOR ATMEGA128

                                    ;***************************************************************************
                                    ;
                                    ; File Name		:'M_rs232.asm"
                                    ; Title			: ATmega128 UART,  RS-232 komunikacios rutinok
                                    ; Date			:2003.02.08.	Lastmod.:[2003.02.08.]
                                    ; Version		:1.0.0
                                    ; Support telephone	:+36-70-333-4034,  Old: +36-30-9541-658 VFX
                                    ; Support fax		:
                                    ; Support Email		:info@vfx.hu
                                    ; Target MCU		:ATmaga128
                                    ;
                                    ;***************************************************************************
                                    ;	D E S C R I P T I O N
                                    ;
                                    ;	Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART)
                                    ;
                                    ;Circular serial I/O buffers, with handshake handling for hardware.
                                    ;Interupt driven, thus 'transparent' to User functions
                                    ;
                                    ;You have a head and tail pointer, a constant that tells the size of the array
                                    ;
                                    ;One thing to note, is that the buffer store routine is only concerned with the
                                    ;tail pointer, and the recall routine is only concerned with the head pointer.
                                    ;Only the buffer init routine is concerned with both pointers!
                                    ;
                                    ;
                                    ;***************************************************************************
                                    ;	M O D I F I C A T I O N   H I S T O R Y
                                    ;
                                    ;
                                    ;       rev.      date      who		why
                                    ;	----	----------  ---		--------------------------------------------
                                    ;	0.01	2001.07.21  VFX		Creation (Base on 8515)
                                    ;	1.00	2003.02.08  VFX		Redesign for Atmega128
                                    ;
                                    ;***************************************************************************
                                    ;
                                    ; Init_UART
                                    ; SendChr
                                    ; SendStr
                                    ;
                                    ;
                                    ;Hardware
                                    ;***************************************************************************
                                    ;*
                                    				;RTS pin , Adas keres DSUB9 7.
                                    .equ	SER_HSO_PORT=PORTD	;Hardware Handshake output port
                                    .equ	SER_HSO_DIR=DDRD	;Hardware Handshake output control
                                    .equ	SER_HSO=7		;Hardware Handshake Output bit
                                    
                                    				;CTS pin , Vetelkezseg nyugtazo DSUB9 8.
                                    .equ	SER_HSI_PORT=PIND	;Hardware Handshake input port
                                    .equ	SER_HSI_DIR=DDRD	;Hardware Handshake input control
                                    .equ	SER_HSI=5		;Hardware Handshake Input bit
                                    
                                    
                                    .MACRO HS_Enabled
                                    		cbi	SER_HSO_PORT,SER_HSO		;Set low, HS to off
                                    .endm
                                    
                                    .MACRO HS_Disabled
                                    		sbi	SER_HSO_PORT,SER_HSO		;Set Hi for Dis
                                    .endm
                                    
                                    
                                    ;**************************************************************************
                                    ;* Const Def
                                    
                                    
                                    ;********************************************************************
                                    ;
                                    ;ASCII Equivalents
                                    ;
                                    .equ	NUL=0x00	;Null
                                    .equ	SOH=0x01	;Start of Header
                                    .equ	STX=0x02	;Start of Text
                                    .equ	ETX=0x03	;End of Text
                                    .equ	EOT=0x04	;End of Transmission
                                    .equ	ENQ=0x05	;Enquiry
                                    .equ	ACK=0x06	;Acknowlege
                                    .equ	BEL=0x07	;Bell
                                    .equ	BS=0x08		;Backspace
                                    .equ	HT=0x09		;Horizontal Tab
                                    .equ	LF=0x0A		;Line Feed
                                    .equ	VT=0x0B		;Vertical Tab
                                    .equ	FF=0x0C		;Form Feed
                                    .equ	CR=0x0D		;Carriage Return
                                    .equ	SO=0x0E		;
                                    .equ	SI=0x0F		;
                                    
                                    .equ	DLE=0x10	;Delete
                                    .equ	XON=0x11	;AKA DC1
                                    .equ	XOFF=0x12	;AKA DC2
                                    .equ	DC3=0x13	;
                                    .equ	DC4=0x14	;
                                    .equ	NAK=0x15	;Negative Acknowlege
                                    .equ	SYN=0x16	;Sync
                                    .equ	ETB=0x17	;
                                    .equ	CAN=0x18	;Cancel
                                    .equ	EM=0x19		;
                                    .equ	SUB=0x1A	;End of File
                                    .equ	ESC=0x1B	;
                                    .equ	FS=0x1C		;Field Separator
                                    .equ	GS=0x1D		;Group Separator
                                    .equ	RS=0x1E		;Record Separator
                                    .equ	US=0x1F		;
                                    
                                    
                                    ;From the data sheet:BAUD = XTAL/(16*(UBRR+1))
                                    ;Rearranging you get:UBRR = XTAL/(16*BAUD) - 1
                                    ;
                                    ;This would work except that any fraction will be truncated.
                                    ;For least error we want to round off the result.
                                    ;So we add 1/2 as follows: UBRR = XTAL/(16*BAUD) - 1 + 0.5
                                    ;Combining the -1 and the +0.5 we can rewrite this as follows:
                                    ;
                                    ;UBRR = INT(XTAL/(16*BAUD) - 0.5)
                                    
                                    .equ	Rx_Buffer_Length = 24
                                    .equ	Tx_Buffer_Length = 32
                                    
                                    .equ	SendROMTXT = 0x02		;RS232 Tx func. Send ROM text to RS232
                                    
                                    
                                    .equ	FlSending = 0b00000001		;Tx Send running
                                    .equ	FlSendROM = 0b00000010		;Tx Send ROM TXT Flag
                                    
                                    
                                    ;***************************************************************************
                                    .DSEG
                                    
                                    Rx_Buffer:
                                    Rx_Head:	.byte 1
                                    Rx_Tail:	.byte 1
                                    Rx_Data:	.byte Rx_Buffer_Length
                                    
                                    Tx_Buffer:
                                    Tx_Head:	.byte 1
                                    Tx_Tail:	.byte 1
                                    Tx_Data:	.byte Tx_Buffer_Length
                                    
                                    
                                    UARTFlg:	.byte 1			;UART Flags
                                    ROMTXT:		.byte 3			;ROM TXT kuldeskor az aktualis ROM pozicio cime
                                    
                                    
                                    
                                    ;*************************************************************************
                                    ;*  Text Const
                                    ;*
                                    .CSEG
                                    
                                    
                                    ;************************************************************************
                                    ;** Init_UART1
                                    ;** Set up the inital states for the buffers, and make sure the handshake
                                    ;** is turned on (Not the Shaddap state), so we can talk.
                                    ;**
                                    ;**
                                    ;************************************************************************
                                    Init_UART1:	ldi	R16,0
                                    		sts	Tx_Tail,R16
                                    		sts	Tx_Head,R16
                                    		sts	Rx_Tail,R16
                                    		sts	Rx_Head,R16
                                    		sts	UARTFlg,R16
                                    
                                    		sts	CMD_Len,R16
                                    		sts	CMD_Pos,R16
                                    
                                    						;Set up Hardware HS I/O bits
                                    		sbi	SER_HSO_DIR,SER_HSO	;Set as output
                                    		HS_Enabled
                                    
                                    		cbi	SER_HSI_PORT,SER_HSI	;Set as input, Pull-up
                                    		cbi	SER_HSI_DIR,SER_HSI
                                    
                                    		ldi	R16,High(SYSCLK/(16*BaudSpeed1)-1)
                                    		sts	UBRR1H,R16
                                    		ldi	R16,Low(SYSCLK/(16*BaudSpeed1)-1)
                                    		sts	UBRR1L,R16		;BaudRate Gen.
                                    
                                    		ldi	R16,0b00000000		;RXCn, TXCn, UDREn, FEn, DORn, UPEn, U2Xn, MPCMn
                                    		sts	UCSR1A,R16
                                    
                                    		ldi	R16,0b11011000		;RXCIE,TXCIE,UDRIE,RXEN,TXEN,UCSZn2,RXB8,TXB8
                                    		sts	UCSR1B,R16
                                    
                                    		ldi	R16,0b00000110		;–, UMSELn, UPMn1, UPMn0, USBSn, UCSZn1, UCSZn0, UCPOLn
                                    		sts	UCSR1C,R16
                                    		ret
                                    
                                    ECopyr:	  	.DB "(C) 2003 VFX ATmega128 Service Terminal [2003.02.08.]",CR
                                    	  	.DB "Firmware version ",MAJOR_REV,".",MINOR_REV,MINOR_REVB," "
                                    	  	.DB "Latest Upd.: 2003.05.01.",CR,0
                                    
                                    
                                    ;***********************************************
                                    ;* Megnezi, hogy kell-e ujrainditani a Tx muveletet
                                    
                                    TxRunning:	lds	ZL,Tx_Head
                                    		lds	ZH,Tx_Tail
                                    		cp	ZL,ZH			;ha azonosak akkor nincs mit tenni
                                    		breq	TxRun1
                                    		lds	ZL,UARTFlg
                                    		andi	ZL,FlSending		;Tx folyamatban?
                                    		brne	TxRun1			;ha igen nincs mit tenni
                                    		rjmp	USART1_TXC
                                    TxRun1:		ret
                                    
                                    
                                    
                                    ;***************************************************************************
                                    ;***************************************************************************
                                    ;***************************************************************************
                                    ;**   UART TX Functions
                                    ;***************************************************************************
                                    ; kod			  Bufferbe 		    Osszesen
                                    ; 0x02 - send ROM TXT ->  0xE0, 0x02, low addr, hi addr ; 4 byte
                                    ; 0xE0 - send 0xE0    ->  0xE0, 0xE0 			; 2 byte
                                    
                                    
                                    ;************************************************************************
                                    ;** Calc Tx Buffer Free Space
                                    ; In:	-
                                    ; Out:	R18 - Tx_Tail
                                    ;	R19 - Tx_Head
                                    ;	R20 - Free Space in Tx Buffer
                                    ; Alt:  R21
                                    ;
                                    ; Tail < Head -> Free= LEN+Tail-Head-1
                                    ; Tail = Head -> Free= LEN
                                    ; Tail > Head -> Free= Tail-Head-1
                                    ;
                                    FreeInTxBuff:	lds	R19,Tx_Head
                                    		lds	R18,Tx_Tail
                                    		ldi	R20,Tx_Buffer_Length
                                    		mov	R21,R18
                                    		sub	R21,R19
                                    		breq	FreeInTx1		;T=H, Free= Tx_Buffer_Length
                                    		brcs	FreeInTx2
                                                    clr	R20
                                    FreeInTx2:	add	R20,R21
                                    		dec	R20
                                    FreeInTx1:	ret
                                    
                                    ;************************************************
                                    ;* The RS232 Tx FIFO manager ROM TEXT		*
                                    ;* In: (R16, R17) address word of text (L,H)		*
                                    ;* Out: c=1 hiba				*
                                    ;************************************************
                                    SendStr:	rcall	FreeInTxBuff		;R18,R19-t is beallitja
                                    		cpi	R20,4
                                    		brcs	ExitwError		;ha <4 nincs eleg hely! Hiba!
                                    
                                    		clr	R18			;R18=0
                                    		ldi	ZL,low(Tx_Data)		;Z to the addr of txbuffer (FIFO)
                                    		ldi	ZH,high(Tx_Data)
                                    		add	ZL,R19
                                    		adc	ZH,R18			;add address offset...  z = @Buf[Tx_head]
                                    		push	R16
                                    		ldi	R16,0xE0		;Alternative function indicator
                                    
                                    		cli
                                    
                                    		rcall	StoreChar
                                    		ldi	R16,SendROMTXT		;Buf[Tx_head]=SendROMTXT indicate Send ROM TXT
                                    		rcall	StoreChar
                                    		pop	R16
                                    		rcall	StoreChar		;Buf[Tx_head]=RomTXT low address
                                    
                                    		sei
                                    
                                    		mov	R16,R17			;Store RomTXT high address
                                    		rcall	StoreChar
                                    		sts	Tx_Head,R19		;Store new pointer
                                    
                                    		rcall	TxRunning
                                    
                                    		clc				;Nincs hiba
                                    		ret
                                    
                                    ExitwError:	sec				;Return with error
                                    		ret
                                    
                                    
                                    SendStrW:	rcall	SendStr
                                    		brcs	SendStrW
                                    		ret
                                    
                                    
                                    
                                    ;************************************************
                                    ;* The RS232 Tx FIFO manager Send CHAR		*
                                    ;* in: R16 char 				*
                                    ;* out c=1 hiba					*
                                    ;************************************************
                                    SendChr:	rcall	FreeInTxBuff		;R18,R19-t is beallitja
                                    		cpi	R20,2
                                    		brcs	ExitwError		;ha <1 nincs elg hely! Hiba!
                                    
                                    		clr	R18			;R18=0
                                    		ldi	ZL,low(Tx_Data)		;Pointer to the txbuffer (FIFO)
                                    		ldi	ZH,high(Tx_Data)
                                    		add	ZL,R19
                                    		adc	ZH,R18			;add address offset...  z = @Buf[txhead]
                                    
                                    		cpi	R16,0xE0		;Alternative kod?
                                    		brne	only1char		;ha igen akkor ketszer kell atkuldeni!!
                                    		rcall	StoreChar
                                    only1char:	rcall	StoreChar
                                    		sts	Tx_Head,R19
                                    
                                    		rcall	TxRunning
                                    
                                    		clc				; Nincs hiba
                                    		ret
                                    
                                    SendChrW:	push	ZL
                                    		push	ZH
                                    		rcall	SendChr
                                    		pop	ZH
                                    		pop	ZL
                                    		brcs	SendChrW
                                    		ret
                                    
                                    
                                    ;***********************************************
                                    ; Subrutin for SendROMTXT & SendChar
                                    
                                    StoreChar:	st	Z+,R16			;Store char
                                    		inc	R19
                                    		cpi	R19,Tx_Buffer_Length
                                    		brcs	StoreC1			;TxHead
                                 

Programming the AVR Microcontrollers in Assember Machine Language

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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated IC Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language