;***************************************************************************
;
; File Name :'twi.asm"
; Title : I2C (TWI) Hardware
; Date :2003.04.29. Lastmod.:[2003.04.29.]
; Version :1.0.0
; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX
; Support fax :
; Support Email :info@vfx.hu
; Target MCU :ATmaga128
;
;***************************************************************************
; D E S C R I P T I O N
;
;
;
;***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
;
;
; rev. date who why
; ---- ---------- --- --------------------------------------------
; 0.01 2003.04.29 VFX Creation
;
;***************************************************************************
;
;
;
;Hardware
;***************************************************************************
;*
;**************************************************************************
;* Const Def
;
;Bit Rate Generator in Master Mode
;TWBR = Value of the TWI Bit Rate Register
;TWPS = Value of the prescaler bits in the TWI Status Register
;
;Note: TWBR should be 10 or higher if the TWI operates in Master mode.
; If TWBR is lower than 10, the master may produce an incorrect output on SDA
; and SCL for the reminder of the byte.
;
; SCL = SYSCLK/(16+2*TWBR*4^TWPS) , TWPS= 0..3, TWBR= 0..255
;
; we use 100kHz I2C Bus & TWPS = 0, always for LOW Power
.EQU SCL_Freq = 100000 ;Hz
.EQU TWI_SlaveAddress = 0xFE ;Slave Address is FECO :)
.equ TWI_WriteByte = 0x00 ;Send Byte
.equ TWI_WriteRAW = 0x01 ;Send Blokk of data
.equ TWI_ReadByte = 0x02 ;Read Byte
.equ TWI_ReadRAW = 0x03 ;Read Block of data
;***************************************************************************
.DSEG
TWI_CTL: .byte 2 ;Address of TWI IO Control Blokk
TWI_Count: .byte 1 ;Byte counter for TWI
TWI_Slave: .byte 1 ;Slave Address
TWI_ADR: .byte 1 ;Slave internal Address
TWI_Flag: .byte 1 ;0. = 1 TWI in use
TWI_SADR: .byte 2 ;TWI State Machin Address
;*************************************************************************
;* Code
;*
.CSEG
;*************************************************************************
;* Init TWI Device, Clear TWI_CTL
;
TWI_Init:
ldi R16,Low(TWIRET)
sts TWI_SADR+0,R16
ldi R16,High(TWIRET)
sts TWI_SADR+1,R16
ldi R16,SYSCLK/(2*SCL_Freq)-8 ;TWI Bit Rate Register - TWBR
sts TWBR,R16
ldi R16,0b00000101 ;TWI Control Register – TWCR
sts TWCR,R16 ;7 – TWINT: TWI Interrupt Flag
;6 – TWEA: TWI Enable Acknowledge
;5 – TWSTA: TWI START Condition
;4 – TWSTO: TWI STOP Condition
;3 - TWWC: TWI Write Collision Flag
;2 – TWEN: TWI Enable
;1 – Res: Reserved Bit
;0 – TWIE: TWI Interrupt Enable
ldi R16,0b11111000 ;TWI Status Register – TWSR
sts TWSR,R16 ;7..3 – TWS: TWI Status
;2 – Res: Reserved Bit
;1..0 – TWPS: TWI Prescaler Bits
ldi R16,TWI_SlaveAddress ;TWI (Slave) Address Register
sts TWAR,R16
clr R16
sts TWI_Flag,R16
ret
;*************************************************************************
;* Start TWI Comunication in Master Mode
; In: X - Address of IO_CTR Block
;
; R17 - count of byte
; R18 - Slave Address
; R19 - Internal Address of Slave
; Out: c = 1 error
;
TWI_StartRead:
rcall WaitToTWI
ldi R16,Low(RBlock0)
sts TWI_SADR+0,R16
ldi R16,High(RBlock0)
sts TWI_SADR+1,R16
TWI_Common:
sts TWI_CTL+0,XL
sts TWI_CTL+1,XH
sts TWI_Count,R17
sts TWI_Slave,R18
sts TWI_ADR,R19
lds R16,TWI_Flag
ori R16,1 ;TWI in use!
andi R16,0b11111101 ;TWI no error
sts TWI_Flag,R16
ldi R16,0b11100101
sts TWCR,R16 ;7 – TWINT: TWI Interrupt Flag
;6 – TWEA: TWI Enable Acknowledge
;5 – TWSTA: TWI START Condition
;4 – TWSTO: TWI STOP Condition
;3 – TWWC: TWI Write Collision
;2 – TWEN: TWI Enable
;1 – Res: Reserved
;0 – TWIE: TWI Interrupt Enable
TWIRET:
ret
;*************************************************************************
;* Start TWI Comunication in Master Mode - Write!
; In: X - Address of IO_CTR Block
; R17 - count of byte
; R18 - Slave Address
; R19 - Internal Address of Slave
; Out: c = 1 error
;
TWI_StartWrite:
rcall WaitToTWI
ldi R16,Low(WBlock0)
sts TWI_SADR+0,R16
ldi R16,High(WBlock0)
sts TWI_SADR+1,R16
rjmp TWI_Common
;*************************************************************************
;* TWI interrupt
;*
TWI: ; Two-wire Serial Interface Interrupt Handler
push ZL
push ZH
in ZL,SREG ;preserve main OS status reg.
push ZL
push R16
push R0
push R17
in ZL,RAMPZ
push ZL
lds R16,TWSR ;Load TWI Status
andi R16,0b11111000 ;csak a status marad
lds ZL,TWI_SADR+0
lds ZH,TWI_SADR+1
icall
pop ZL
out RAMPZ,ZL
pop R17
POP R0
POP R16
POP ZL
OUT SREG,ZL
POP ZH
POP ZL
RETI
;************************************************************************************************************
;*** R E A D B L O C K
;***
;
;***********************
; Read Block of data - State 0
; Start bit sended
RBlock0:
cpi R16,0x08 ;A START condition has been transmitted
breq Rbl0
cpi R16,0x10 ;A Repeated START condition has been transmitted
breq Rbl0
rjmp TWI_ReadError
Rbl0:
lds R16,TWI_Slave
andi R16,0b11111110 ;Write SLA
sts TWDR,R16 ;Send Slave Address
ldi R16,Low(RBlock1)
sts TWI_SADR+0,R16
ldi R16,High(RBlock1)
sts TWI_SADR+1,R16
ldi R16,(1< Send slave internal address
RBlock1:
cpi R16,0x18 ;SLA+W has been transmitted
breq RBl1
rjmp TWI_ReadError
RBl1:
lds R16,TWI_ADR
sts TWDR,R16 ;Send Slave Internal Address
ldi R16,Low(RBlock2)
sts TWI_SADR+0,R16
ldi R16,High(RBlock2)
sts TWI_SADR+1,R16
ldi R16,(1< Repeated Satrt send
RBlock2:
cpi R16,0x28 ;SlaveAddress sended + ACK received
breq Rbl21
rjmp TWI_ReadError
Rbl21:
ldi R16,Low(RBlock3)
sts TWI_SADR+0,R16
ldi R16,High(RBlock3)
sts TWI_SADR+1,R16
ldi R16,(1< Send SLA+R
RBlock3:
cpi R16,0x10 ;Repeated Start sended + ACK received
breq RBl31
rjmp TWI_ReadError
RBl31:
lds R16,TWI_Slave
ori R16,1 ;Write SLA+R
sts TWDR,R16 ;Send Slave Address
ldi R16,Low(RBlock4)
sts TWI_SADR+0,R16
ldi R16,High(RBlock4)
sts TWI_SADR+1,R16
ldi R16,(1< Read data byte
RBlock4:
cpi R16,0x40 ;SLA+R send + ACK received
brne TWI_ReadError
lds R16,TWI_Count
cpi R16,1
breq TWILAstByte
ldi R16,Low(RBlock5)
sts TWI_SADR+0,R16
ldi R16,High(RBlock5)
sts TWI_SADR+1,R16
ldi R16,(1< Send slave internal address
WBlock1:
cpi R16,0x18 ;SLA+W has been transmitted
breq WBl1
rjmp TWI_WriteError
WBl1:
lds R16,TWI_ADR
sts TWDR,R16 ;Send Slave Internal Address
ldi R16,Low(WBlock2)
sts TWI_SADR+0,R16
ldi R16,High(WBlock2)
sts TWI_SADR+1,R16
ldi R16,(1< Write data
WBlock2:
cpi R16,0x28 ;Data byte has been transmitted + ACK received
breq WB12
rjmp TWI_WriteError
WB12: ;Send data byte continous
lds ZL,TWI_CTL+0
lds ZH,TWI_CTL+1
ld R0,Z+
sts TWDR,R0 ;next data byte
sts TWI_CTL+0,ZL
sts TWI_CTL+1,ZH
lds R16,TWI_Count
cpi R16,1
breq TWI_WriteLastByte
dec R16
sts TWI_Count,R16
ldi R16,(1<
Programming the AVR Microcontrollers in Assember Machine Language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers.
The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders:
Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links
6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory
mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes
for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after
cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities
than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as
EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer
a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K
In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language
Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan,
at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16
bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed
by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have
on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different
addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than
I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as
EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer
a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K
In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language
Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan,
at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16
bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed
by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have
on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different
addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than
I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as
EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer
a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K
In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language
Atmel AVR machine programming language