The attached code shows how to connect, initialise and drive a 44780-based LCD in 4-bit mode.
The 2 additional pins are probably reserved for a backlight option - they were on my display from Dontronics.
;-----------------------------------------------------------------
;
; Name: LCDMain.asm
; Title: Main routine for driving Hitach LCD display
; Version: 1.0
; Last updated: 2001.06.04
; Target: AT90S2313
;
;-----------------------------------------------------------------
;
; DESCRIPTION
;
; Driver for Hitachi HD44780-based LCD display
;
; Display is wired to Port B. Each individual pin on the display
; is wired as follows:
;
; Pin 1 - Vss GND Supply ground
; Pin 2 - Vdd VTG Supply +ve
; Pin 3 - Vee GND Contrast adjust = maximum
; Pin 4 - RS PB4 Command/data
; Pin 5 - R/W PB5 Read/write
; Pin 6 - EN PB6 Enable
; Pin 7 - DB0 GND Data bit 0 = 0
; Pin 8 - DB1 GND Data bit 1 = 0
; Pin 9 - DB2 GND Data bit 2 = 0
; Pin 10- DB3 VTG Data bit 3 = 1 to indicate 2-line display at startup
; Pin 11- DB4 PB0 Data bit 4 = PortB:0
; Pin 12- DB5 PB1 Data bit 5 = PortB:1
; Pin 13- DB6 PB2 Data bit 6 = PortB:2
; Pin 14- DB7 PB3 Data bit 7 = PortB:3
; Pin 15- (if present) No connection
; Pin 16- (if present) No connection
;
;-----------------------------------------------------------------
.nolist
.include "2313def.inc"
.list
;-----------------------------------------------------------------
;
; General purpose registers
.def rRETURN =r0 ; return value from functions
.def rZERO =r1
.def rSCRATCH =r7
.def rSCRATCH2 =r8
.def rSCRATCH3 =r9
.def rSCRATCH4 =r10
.def rISCRATCH =r11 ; for use in interrupt routines
.def rISCRATCH2 =r12 ; ditto
.def rISCRATCH3 =r13 ; ditto
.def rISCRATCH4 =r14 ; ditto
.def rISREGSAVE =r15 ; sreg saved here in interrupts
.def rTEMP =r16
.def rTEMP2 =r17
.def rITICK =r18 ; Decreasing tick, used for delays
.def rITEMP =r19
.def rPARAM1 =r20
.def rPARAM2 =r21
.def rLOOPI =r22 ; loop counters
.def rLOOPJ =r23
;-----------------------------------------------------------------
;
; Equates
;-----------------------------------------------------------------
;
; IO Port Bits
.equ mDATA =0x0F
.equ bRS =4
.equ bRW =5
.equ bEN =6
;-----------------------------------------------------------------
;
; Timings
;
; We need a multiple of 100Hz for the clock tick, so for 4MHz
; this equates to 40,000 clock cycles, and for a 3.6864MHz clock,
; this is 36,864 cycles. Given the prescaler values available
; on counter/timer 0, we get the following:
;
; Divider Counts 4MHz Counts 3.7MHz In range?
; Clk/8 5000 4608 No (greater than 255)
; Clk/64 625 576 No (greater than 255)
; Clk/64 125 for 500Hz 144 for 400Hz Yes
;
; The actual values loaded into the registers are these values
; subtracted from 256, since we are counting up, and the clock
; interrupt happens when the clock register overflows to 256.
.equ TIMERSCALE =$03 ; Clk/64
; Timer value for 3.6864 MHz clock
.equ TIMERVALUE = (256-144)
.equ TICKVALUE = 4 ; 4 x 400Hz ticks = 100Hz clock
; Timer value for 4 MHz clock
; .equ TIMERVALUE = (256-125)
; .equ TICKVALUE = 5 ; 5 x 500Hz ticks = 100Hz clock
;-----------------------------------------------------------------
;
; Variables
.dseg
tickcount: .byte 1 ; clock count to 4 or 5 for centiseconds
centi: .byte 1 ; centisecond count
second: .byte 1 ; second count
minute: .byte 1 ; minute
hour: .byte 1 ; hour
day: .byte 1 ; day
;-----------------------------------------------------------------
;
; Interrupt service vectors
.cseg
.org 0
rjmp Reset ; Reset vector
.org OVF0addr
rjmp Timer0 ; Timer tick
;-----------------------------------------------------------------
;
; Start of actual code.
;
;-----------------------------------------------------------------
;
; Timer 0 overflow - decreases tick count in tickcount until it
; reaches 0, then ripples the count along to the next biggest
; counter, all the way up to the "days" count.
Timer0: in rISREGSAVE,SREG ; store status register
ldi rITEMP,TIMERVALUE ; reset counter
out TCNT0,rITEMP ; to start counting again
mov rISCRATCH,YL ; store Y register
mov rISCRATCH2,YH ; since we will be using it
dec rITICK ; decrease register tick count
ldi YL,low(tickcount) ; Y points to tick count
clr YH
ld rITEMP,Y ; get tick count
inc rITEMP ; increment it
cpi rITEMP,TICKVALUE ; is it the target value yet?
brne Timer0_Done ; no... exit immediately
clr rITEMP ; yes - clear it and store it again
st Y+,rITEMP ; increment Y to point to centiseconds
;
; We get through to here once every 4 or 5 timer ticks, in
; other words, 100 times every second.
;
ld rITEMP,Y ; load centiseconds
inc rITEMP ; increment
cpi rITEMP,100 ; and check for overflow
brne Timer0_Done ; no... exit immediately
clr rITEMP ; else reset to 0
st Y+,rITEMP ; store, and increment Y to point to seconds
ld rITEMP,Y ; load seconds
inc rITEMP ; increment
cpi rITEMP,60 ; check for overflow
brne Timer0_Done ; no... exit immediately
clr rITEMP ; else reset to 0
st Y+,rITEMP ; store, and increment Y to point to minutes
ld rITEMP,Y ; load minutes
inc rITEMP ; increment
cpi rITEMP,60 ; check for overflow
brne Timer0_Done ; no... exit immediately
clr rITEMP ; else reset to 0
st Y+,rITEMP ; store, and increment Y to point to hours
ld rITEMP,Y ; load hours
inc rITEMP ; increment
cpi rITEMP,24 ; check for overflow
brne Timer0_Done ; no... exit immediately
clr rITEMP ; else reset to 0
st Y+,rITEMP ; store, and increment Y to point to days
ld rITEMP,Y ; load days
inc rITEMP ; and increment
;
; However we get here, the most recently incremented value is in rITEMP,
; and Y points to where we got it from.
;
Timer0_Done:
st Y,rITEMP ; store valid value back again
mov YL,rISCRATCH ; restore saved Y pointer
mov YH,rISCRATCH2
out SREG,rISREGSAVE ; restore status register
reti ; and return from interrupt, done.
;-----------------------------------------------------------------
;
; WaitTick
; Waits for between rPARAM1 and rPARAM1+1 timer ticks, depending
; on exactly when the next tick is about to happen. Each tick takes
; 20ms on a 4MHz clock, or 25ms on a 3.6864MHz clock. This is enough
; to act as a timed delay for those commands which take more than
; the 40us "standard" delay.
WaitTick:
inc rPARAM1
mov rITICK,rPARAM1
WaitTick_Loop:
and rITICK,rITICK
brne WaitTick_Loop
ret
;-----------------------------------------------------------------
;
; Reset vector - generic system.
Reset:
ldi rTEMP,RAMEND-1 ; Set stack to end of RAM
out SPL,rTEMP
; Get the timer going
ldi rTEMP,(1< out TIMSK,rTEMP
ldi rTEMP,TIMERVALUE ; timer value
out TCNT0,rTEMP
ldi rTEMP,TIMERSCALE ; clock prescaler for Timer 0
out TCCR0,rTEMP
;
; And allow timer interrupts
;
sei
; Set port B to all output, all 0.
ldi rTEMP,$00
out PORTB,rTEMP
ldi rTEMP,$FF
out DDRB,rTEMP
;
; Now initialize the display
;
rcall InitDisplay
;
; And reset the displayed time to 00 00:00:00.00
;
clr rTEMP
sts tickcount,rTEMP
sts centi,rTEMP
sts second,rTEMP
sts minute,rTEMP
sts hour,rTEMP
sts day, rTEMP
ldi rPARAM1,0x00
rcall LCDGoto ; go to display position 0
ldi ZL,low(String*2)
ldi ZH,high(String*2)
rcall LCDString ; and send string
Loop:
ldi rPARAM1,0x40
rcall LCDGoto ; go to display position 0x40 (2nd line)
lds rPARAM1,day ; get the day
rcall LCDNumber ; output as a 2-digit number
ldi rPARAM1,' ' ; followed by a space,
rcall WriteData
lds rPARAM1,hour ; then the hour
rcall LCDNumber ; as a 2 digit number
ldi rPARAM1,':' ; followed by a colon
rcall WriteData
lds rPARAM1,minute ; then the minute
rcall LCDNumber ; as a 2 digit number
ldi rPARAM1,':' ; followed by a colon
rcall WriteData
lds rPARAM1,second ; then the second
rcall LCDNumber ; as a 2 digit number
ldi rPARAM1,'.' ; followed by a decimal point
rcall WriteData
lds rPARAM1,centi ; and finally the 1/100ths of a second
rcall LCDNumber ; yes, as a 2 digit number.
lds rTEMP,centi ; get the centiseconds "then"
Wait: lds rTEMP2,centi ; get the centiseconds "now"
cp rTEMP,rTEMP2 ; same?
breq Wait ; yes... go round again and wait till it changes
rjmp Loop ; then display all over again, for ever
;-----------------------------------------------------------------
;
; InitDisplay
; Initialize display as shown in data sheet.
InitDisplay:
; Initial power-up delay
; Wait for 15ms or more (100-125ms in fact)
ldi rPARAM1,5
rcall WaitTick
; Send 8-bit mode command
ldi rTEMP2,0x03 ; 8 bit mode indicator
rcall Strobe ; and strobe it out
; Wait again
ldi rPARAM1,1 ; min 20ms delay (4ms + leeway)
rcall WaitTick ; until ready to receive
; Send 8-bit mode command again
ldi rTEMP2,0x03 ; 8 bit mode indicator
rcall Strobe ; and strobe it out
; Wait again
ldi rPARAM1,100 ; 100us
rcall WaitMicro ; until ready to receive
; Now 4-bit mode command to actually place us in 4-bit mode
; as originally required.
ldi rTEMP2,0x02 ; 4 bit mode indicator
rcall Strobe ; and strobe it out
; Wait
ldi rPARAM1,100 ; 100us
rcall WaitMicro ; until ready to receive
;
; We can now use the normal functions for writing data,
; which are designed to work with 4-bit mode data timings
;
; Function set
ldi rPARAM1,0x28 ; 4 bit, dual line
rcall WriteInstruction
; Display on
ldi rPARAM1,0x0E ; display on, cursor on, no blink.
rcall WriteInstruction
; Display clear
ldi rPARAM1,0x01
rcall WriteInstruction
ldi rPARAM1,1 ; min 20ms delay (4ms + leeway)
rcall WaitTick ; until ready to receive
; Entry mode set
ldi rPARAM1,0x06 ; Advance cursor, no shift
rcall WriteInstruction
ret
;-----------------------------------------------------------------
;
; LCDGoto
; Go to character position rPARAM1
LCDGoto:
ori rPARAM1,0x80
rjmp WriteInstruction
;-----------------------------------------------------------------
;
; LCDNumber
; Write number from 00 to 99 at current position
LCDNumber:
mov rPARAM2,rPARAM1
ldi rTEMP,'0'
LCD10s: subi rPARAM2,10
brmi LCD1s
inc rTEMP
rjmp LCD10s
LCD1s: mov rPARAM1,rTEMP
rcall WriteData
subi rPARAM2,-(0x3A)
mov rPARAM1,rPARAM2
rjmp WriteData
;-----------------------------------------------------------------
;
; LCDString
; Write string at Z from flash to LCD at current position
LCDString:
lpm
and r0,r0
breq LCDString_End
adiw ZL,1
mov rPARAM1,r0
rcall WriteData
rjmp LCDString
LCDString_End:
ret
;-----------------------------------------------------------------
;
; WriteData
; Write rPARAM1 as data
WriteData:
ldi rTEMP,(1< rjmp Write
;-----------------------------------------------------------------
;
; WriteInstruction
; Write rPARAM1 as instruction
WriteInstruction:
ldi rTEMP,0
Write:
mov rTEMP2,rPARAM1
swap rTEMP2
andi rTEMP2,$0F
or rTEMP2,rTEMP
rcall Strobe
mov rTEMP2,rPARAM1
andi rTEMP2,$0F
or rTEMP2,rTEMP
rcall Strobe
rjmp Wait40
;-----------------------------------------------------------------
;
; Strobe
; Output rTEMP2 to PortB and then strobe the enable line
Strobe:
out PORTB,rTEMP2
nop
nop
nop
sbi PORTB,bEN
nop
nop
nop
cbi PORTB,bEN
ret
;-----------------------------------------------------------------
;
; Wait40, WaitMicro
; Wait 40 (or rPARAM1) microseconds
Wait40:
ldi rPARAM1,40 ; 40uS
WaitMicro: ; 4 cycles
nop ; per loop
dec rPARAM1 ; at 4 MHz
brne WaitMicro ; = 1 uS per loop
ret
;-----------------------------------------------------------------
;
; ReadStatus
; Read Status into rReturn.
ReadStatus:
ldi rTEMP,(1< rjmp Read
;-----------------------------------------------------------------
;
; ReadData
; Read Data into rReturn
ReadData:
ldi rTEMP,(1<
Read: out PORTB,rTEMP
nop
sbi PORTB,bEN
nop
nop
in rTEMP,PINB
cbi PORTB,bEN
andi rTEMP,0x0F
swap rTEMP
sbi PORTB,bEN
mov rRETURN,rTEMP
nop
in rTEMP,PINB
cbi PORTB,bEN
andi rTEMP,0x0F
or rRETURN,rTEMP
rjmp Wait40
;-----------------------------------------------------------------
;
; WaitBusy
; Waits until device is not busy
WaitBusy:
rcall ReadStatus
and rRETURN,rRETURN
brmi WaitBusy ; if bit 7 still set, go round again
ret
;-----------------------------------------------------------------
;
; Strings to display
String:
.db "Time since start:", 0
;-----------------------------------------------------------------
Programming the AVR Microcontrollers in Assember Machine Language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers.
The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders:
Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links
6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory
mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes
for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after
cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities
than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as
EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer
a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K
In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language
Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan,
at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16
bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed
by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have
on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different
addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than
I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as
EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer
a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K
In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language
Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan,
at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16
bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed
by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have
on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different
addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than
I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as
EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer
a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K
In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language
Atmel AVR machine programming language